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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (123378)8/31/2000 1:20:05 PM
From: Scumbria  Read Replies (1) | Respond to of 1570553
 
John,

After all, with the deep pipeline, you probably have some extra cycles (5?, 10?) to get the data from L2 if its not in L1.

The pipeline is designed to receive L1 data in two cycles. Any additional cycles cause bubbles. One bubble per access reduces performance by 50%. Two bubbles is a 67% hit. Three bubbles is a 75% hit.

In other words, on a high frequency CPU, a small L1 cache is totally unacceptable.

Scumbria


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