SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Road Walker who wrote (123391)8/31/2000 2:15:11 PM
From: Scumbria  Read Replies (1) | Respond to of 1570744
 
John,

I'm not saying that Intel's engineers are incompetent, just their architects.

If, as you say, the clock speed was sacrificed, then maybe Intel feels that future applications won't need a lot more clock speed.

The only reason to build a deep pipeline is for clock speed. They seem to have compromised this goal by trying to improve IPC with the double speed ALU.

The 8K 2-cycle cache is really a mystery. The small cache hurts IPC and helps frequency. The 2-cycle access time improves IPC, but hurts frequency. What were they trying to accomplish?

Scumbria