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To: EricRR who wrote (7165)8/31/2000 2:49:11 PM
From: ScumbriaRead Replies (1) | Respond to of 275872
 
Ratbert,

X86 has a lousy FPU architecture. Some new RISC processors don't even do integer multiplies in the integer ALU, because FPU hardware tends to be faster.

ALU latency needs to be viewed in terms of a pipeline. If you can complete one instruction per clock, the absolute latency is meaningless.

Scumbria