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To: Tenchusatsu who wrote (109122)	8/31/2000 3:29:52 PM
From: chic_hearne	Read Replies (1) \| Respond to of 186894

Re: He's asking for a little context behind that very impressive-sounding 45 GB/sec figure. I guess he's not very familiar with the POWER4 architecture. Tench, Do you know of any other public documents on the POWER4 besides last October's Microprocessor report? I can't quote most of the stuff I have available to me. I think reading that report will give anyone a pretty good idea about the chip though. chic chips.ibm.com

To: Tenchusatsu who wrote (109122)	8/31/2000 4:51:04 PM
From: Rob Young	Read Replies (1) \| Respond to of 186894

Tench, Good overview but to add one wrinkle here that you overlooked. You are mostly touching on the on-chip memory switch. Couple that with the directory based cache that allows a very low latency L2 hit to bypass a global switch (if you will) but route directly from L2 to L2 via the mesh as you describe. Why 16 as a choice? Most hops are 2. When you add up the latency for those 2 hops you are still doing much better than an L3 hit and of course main memory. So in a sense you would have a system with 24 MB of L2 per CPU. A stretch? Somewhat ... but not much of one. Go out and read the earlier referenced papers or some detail from MPR: alphapowered.com Slide 14 and others show the P2P nature Regarding interconnect... not sure.. they can and will go higher. Rumor has it Marvel is 64 CPUs (solid rumor) but that puts remote L2 several hops away.. still better than main memory though !! ;-) Rob