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To: Petz who wrote (7231)	8/31/2000 9:41:13 PM
From: ptanner	Respond to of 275872

John, Re: P3, P4, and T-Bird transistors vs. chip area I believe the on-chip cache is denser than logic components so this is part of the reason for the difference between the T-Bird (and Intel's cache, while reportedly top of the line in performance is lower-density than other designs). However, the P4 vs P3 is something that I have been wondering about. Hopefully the technically knowledgeable here will provide some thoughts. -PT

To: Petz who wrote (7231)	8/31/2000 11:40:22 PM
From: Scumbria	Respond to of 275872

John, Cell based design is the only sensible approach these days. It allows for much faster time to market, much faster bug fixes, timing fixes, easier floorplanning. Intel's full custom methodology is a serious liability, and is a major cause of the time to market problems they are experiencing. Scumbria

To: Petz who wrote (7231)	9/1/2000 12:47:31 AM
From: Joe NYC	Read Replies (1) \| Respond to of 275872

John, I would like to preface what I about to say with a disclaimer that I don't know the first think about design of the electronic circuits. But from what I read from people who do have clue, my conclusion about the die size disparity mainly has to do with local interconnect. AMD has it, Intel does not. That is why AMD has a competitive die sizes for standard cell design vs. Intel custom logic. According to SemiconEng Intel tried local interconnect but the results were not good enough to bring it to production - low yields. Regarding cell based design vs. custom logic, according to Dale Laroy, AMD is redesigning Athlon core with custom logic, and the result will be Mustang, Palomino and Morgan. The result of the combination of custom logic and local interconnect is that the upcoming cores will be extremely small, so small that doubling AMD can afford to double L2, and the resulting chip will be smaller than the original using the same process. Another positive side effect of this redesign is that the power consumption will be reduced and it will be possible to achieve higher clock speeds. I hope we will not have the negative side effects that Intel is experiencing (delays, bugs) Joe