Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (109196)	9/1/2000 2:42:35 PM
From: Rob Young	Respond to of 186894

Tench, " P.S. - I forgot to ask earlier. Does the 21364 have an L3 cache? My understanding was that it doesn't have one, nor does it need one because the RDRAM is so close to the processor. " Good question.. I wonder the same. I believe your analysis is correct but I don't know for sure. However, I have seen a strong hint in such a direction. Besides as noted earlier the on-chip L2s act as one big happy L2 so to speak. If initially, Marvel scales to 64 processors you would have an effective 96 MByte of L2 at hand.. so I say no need for L3. Yes, some 4 or 5 hops away but math works out it is a smaller percentage than local or "nearby" L2. Besides all asynchronous routing... That's why I believe the positioning of 21364 pretty much gives us the hint to "no L3 necessary". That is "low-cost" server part pops up often enough. BTW , a minor nit: "Maybe that's why you're slinging mud at Itanium. If your product looks bad, try your darnest to make the competition's product look even worse." Not my product. I just enjoy Alpha and VMS. Best in the industry. Speaking of secrets... both pretty much well kept secrets in a sense. They do have their break-out moments of late (Los Alamos, Pittsburgh, Celera, etc. for Alpha/Tru64). Still waiting on VMS break out moment, maybe soon! Rob