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To: Petz who wrote (7371)9/2/2000 5:36:01 AM
From: BilowRead Replies (1) | Respond to of 275872
 
Hi John Petzinger; My reference was to the article's statement that memory bandwidth has been a system limitation for years. This is obviously not the case, otherwise RDRAM would be kicking butt, and DDR would make Athlons fly like hummingbirds, compared to SDRAM. Were it true, designers would have already gone to point to point DDR with 128-bit wide buses, and we would be buying computers with 6GB/sec memory bandwidths. Engineers are not total morons, but tend to fix bottlenecks pretty well. The current bottleneck is still the processor, and that is a big bottleneck to narrow. It is a fact that increasing your CPU MHz is the more effective way of increasing system performance, rather than increasing the memory bandwidth. This is the simple, perfect, and undeniable proof that the CPU MHz is the bottleneck for the system.

Of course this doesn't apply to synthetic benchmarks, which purposely avoid the cache or branch prediction hardware, etc., but those don't have a lot of use in the real world.

The unfortunate thing about a harvard architecture is that it increases the pincount considerably. It would also increase the motherboard size and cost, and require the user to populate two DIMM channels. But it is not needed to get great performance. That is, having a full harvard architecture would undoubtedly improve performance, as would any other extreme effort to increase memory performance. But for that many dollars, more performance could be gained by putting the money into a better processor (or cache). The fact is that high speed processor design is the hardest nut to crack, and that is where the bottleneck is narrowest. High memory bandwidth is trivial to design, Nvidia's GeForce boards include 5GB/sec memory bandwidth (i.e. 3x PC800) along with entire graphics cards, and the whole thing sells for considerably less than a lone 1.1GHz processor chip. If it were possible to get significant improvements in system design by multiplying the memory bandwidth by 5x, the designs are already complete - use any GeForce 2 DDR card as a template. But the fact is that even tripling the memory bandwidth will not improve system performance significantly. Note that the Nvidia graphics processor does need all that bandwidth (and more), but it is not a general purpose CPU.

The sad fact of processor design (currently) is that the processor is a greedy pig for total cache+memory bandwidth, and that bandwidth can only be supplied by a big, fast, on die cache memory. Off chip is too slow both in bandwidth and in latency. The corresponding glad fact of modern processor design is that after you take care of the sad fact, the external memory bandwidth (and latency) become relatively unimportant to overall system performance. (Unimportant in the current regime. Of course you could have DRAM that took seconds to respond instead of nanoseconds. Then you would again be in trouble. But in the current regime, the processor speed dominates performance, not the external memory bandwidth. And of course disk drive access time is a big factor, and I'm ignoring it here cause it has nothing to do with processor design.)

The above facts must not have been obvious to the guys at Intel who signed the agreements with Rambus long ago.

Of course when DDR comes out look for everybody to be touting what a great bandwidth it has, particularly with the synthetic benchmarks, just like they did for RDRAM, and despite the relatively small system performance improvement. But at least it should be a lot cheaper than RDRAM. I'll buy one.

-- Carl