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To: jim kelley who wrote (52829)	9/8/2000 1:16:53 AM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi all; New EE Times article about trends in memory system design... Elegant use of memory Sep 4, 2000 The unveiling of the Nintendo GameCube recently gave the industry an interesting look at where chip-level architecture may be going in the next few years. ... Like most modern system-on-chip designs, the GameCube includes both a large 24-Mbyte main memory and a variety of specialized memories distributed around the system. But the choices of memory type and location suggest the designers were much more concerned with latency than with raw bandwidth. One indication is the use of large blocks of on-chip memory, provided by NEC's embedded-DRAM process. While embedded DRAM is still a questionable approach to cost reduction, it is well established as an approach to latency control. Another indication is the use of MoSys DRAM, or 1-T SRAM, as the company prefers to call it, not just for local buffers but for the main memory. The MoSys scheme for organizing DRAM gives a combination of DRAM cell size and SRAM-like average latency, once again directly addressing the latency issue. Finally, there is the extensive use of caching, not only for the PowerPC but also for textures. Consistently, Nintendo engineers seem to have used memory type, speed and location to reduce the storage latency for computing and rendering tasks. ... The answer today seems to be on-chip, low-latency specialized memory blocks, not proprietary high-bandwidth external buses. That may be a crucial lesson for the next few years. techweb.com Now just how many "proprietary high-bandwidth external buses" are there in the memory community? Do you suppose the writer is talking about SLDRAM? I'd say he's probably implying RDRAM here. -- Carl