Hi John Walliker; Re: "So you are saying that chips which can be configured for SDRAM or DDR operation would operate the core at different voltages depending on which was selected. Is that really likely?"
Good question! The answer is not at all obvious. With almost any technology, your comment would be dead on, but DRAM are a bit different from most CMOS chips.
Power consumption in SDRAM chips is dominated by the "asynchronous" wires, not the "synchronous" ones. This can be readily noted by observing that x4, x8, and x16 SDRAMs all have nearly identical internal power consumption figures. Those different width SDRAM chips all have the same asynchronous logic (i.e. the array of capacitors), but the synchronous logic is (nearly) proportional to the width. Since internal power doesn't appreciably change between the x4, x8, and x16, it is clear that synchronous power consumption is negligible (other than I/O drive).
The "asynchronous" lines in an SDRAM would be the row and column address lines, as well as the data cell I/O lines. The thing to remember is that these wires are the ones particularly driven during activate, precharge and refresh cycles. When you perform a read or write access to an SDRAM (without auto precharge) none of the asynchronous lines are driven. Instead, the read or write is made against entirely in the synchronous logic. Basically, the synchronous logic consists of a single row of flip flops, along with logic to allow reads and writes at whatever size the memory is organized for. That is, if it is a x8 SDRAM, the bits in that row of FFs can be read or written 8 at a time. But reading or writing those bits has nothing to do with the array of capacitors that make up the storage.
The bandwidth of the SDRAM is a function of the bandwidth of the synchronous logic, it has nothing whatsoever to do with the bandwidth of the memory array's asynchronous lines. [In fact, the bandwidth of the asynchronous lines is monstrously huge, as entire rows are read or written in just a few clock periods.] Instead, the time required to drive the asynchronous lines determines the asynchronous timing specifications of the SDRAM (or RDRAM, for that matter). An example of an asynchronous timing specification is the time between an "activate" and the first data read.
Note to those mom/pops who are getting just a bit lost, but want more explanation (i.e. NightOwl): In order to use a row of SDRAM, you must first "activate" it. This is a command that causes the data on a row of capacitors to be transferred to the synchronous circuitry. From there, you can read or write little chunks of the row. When you are done reading and writing to the row, you must put the row back where it came from. This is done with a "precharge" command. After the precharge command, you can no longer read or write to that row of memory, though I fail to see why you should be unable to read data from that row, as it is still contained in the synchronous logic. Also note that this difference between asynchronous and synchronous logic is a consequence of SDRAM being "synchronous" DRAMs. Plain old DRAMs had all those asynchronous timing parameters, and a few more restrictions having to do with CAS cycle time. The asynchronous timing parameters end up being converted into clock cycle count restrictions in SDRAM, and are responsible for the difference between CAS-2 and CAS-3 DRAM, for instance. This is why you can get a CAS3 PC133 SDRAM to run at CAS2 at a frequency sufficiently lower than 133MHz: The timing restriction is one that is "asynchronous" to the clock. So slowing down the clock has an effect in some ways similar to increasing the minimum number of clocks.
So when they reduce the Vcc for the asynchronous drivers, you would expect to see the asynchronous time delays increase. This wouldn't show up in the peak bandwidth of the part, but instead in the latency figures, as well as stuff like the minimum delay between a precharge and an activate to the same bank. (SDRAMs have multiple regions, called "banks" that do not share asynchronous wire. These regions, therefore, can do things that would normally be incompatible. For instance, one bank could be doing a precharge, which is a write to the capacitors, while another bank is doing an activate. Note that there are restrictions as to which commands can operate when on SDRAM, and these restrictions can prevent the above combination from appearing to happen, but in actuality, since a precharge or activate is an operation that takes multiple clocks, it is a fact that different banks can be doing such incompatible things at the same time. Also note that the number of banks in RDRAM was increased considerably, and that was a substantial cause of the 15% increase in die size.
Anyway, you could avoid most of the latency penalty if you made the drive strength for the asynchronous line drivers depend on whether the chip was to be used at 2.5 volts or 3.3 volts. Note that making this alteration would not increase the power consumption of DDR, when averaged over a clock cycle, as power consumed in (unterminated) CMOS does not depend on driver strength.
The synchronous logic would run slower at 2.5V than 3.3V, but .2u CMOS is much, much faster than is needed to get to 133/266MHz. The clock period limiation is a consequence of the slow PCB environment, not a limitation of the CMOS speed.
I hope this was a good start. I'm sure there's lots left to clear up / discuss.
-- Carl |
