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To: kash johal who wrote (109553)9/8/2000 9:43:07 PM
From: Scumbria  Read Replies (1) | Respond to of 186894
 
Kash,

Going from 10 stages to 20 stages should ideally yield a 2x clock speed improvement.

Clock skew and latch delays are fixed, regardless of pipeline depth. At 1GHz, these take up >25% of the cycle. Throw in the large die size of PIV, and I expect to see about 50% improvement in clock speed.

Why is PIII more expensive than PIV?

Scumbria


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