look at PBD (platform based design) which semis are switching to in order to accommodate wireless SoC adaptations (everything moves to the SoC). you can start here. if you'd like to know more about the authors, could supply such. PBD is not so "new", but when all your semis are now switching to it "NEW" has new meaning (in part to accommodate wireless platform integration)! PBD significantly speeds up time to market for products. The company that integrates with this design methodology first wins. Toshiba wireless division is now a fully PBD wireless operation.
eetimes.com
coware.com
Taking flexibility to the max in platforms
By Karl Van Rompaey, Chief Technologist, CoWare Inc.Santa Clara, Calif.
(08/14/00, 3:33 p.m. EST)
Developing a reusable system-on-chip platform is a big challenge and a huge investment. Designing a platform that is configurable is even more of a challenge. It might take months, even years, to develop a proven reusable, reconfigurable system-on-chip (SoC) platform. By then, the market will have passed you by.
What happens when one block of the platform is swapped out for another? How long is it going to take your design team to develop the new hardware and software interfaces for the new processor, bus or peripheral?
For example, your design might work just fine with an ARM9 processor now, but add a few more features and that ARM9 is going to be stressed. Maybe it's time to move up to a PowerPC, but you know it's going to take months to rework your platform for a new processor.
Redesigning your platform for a new processor can be excruciatingly painful. Most often, you virtually have to start over because the interfaces between the processor and the rest of the chip all need to be redone.
The details of all of the necessary interfaces are often found in manuals that are hard to understand, poorly organized and sometimes missing crucial information. Yet every time a major system element is changed, most designers must go back to the manuals.
Designing a system-on-chip with the right methodology and tools can solve a lot of those interface problems. Key to this design process is a system-level specification that can be debugged and used throughout the design process as a golden functional model. Also key is a capability, called interface synthesis, that significantly speeds design by synthesizing all of the time-consuming creation of hardware and software interfaces.
Using this methodology and tools, STMicroelectronics Inc. (Carrollton, Texas) has been able to cut platform-based design from 24 months to six months and the time required for a derivative platform from 10 weeks to two to three weeks, depending on complexity.
The first step in designing an SoC is to decide what you want to design. By developing a formal specification in C/C++, you avoid a lot of the ambiguity found in specs written in English. Even more important, the specification is executable and can therefore be tested. The environment model serves as a system-level testbench that can be used to verify functionality throughout the implementation process.
While an executable specification ensures that the correct functionality is implemented, certain aspects of the specification, such as performance and power consumption, are highly implementation-dependent.
How do you make these decisions? You refine your model, putting in a processor and testing to see if that processor has the horsepower to deliver all of the functionality required. If that processor seems like overkill or doesn't deliver enough horsepower, you try another.
Sounds easy, doesn't it? However, without the right tools, it's just too time-consuming to test out a design with a particular processor and then swap that processor out for another-or make other critical design tradeoffs. Once the processor decision has been made, it is an important commitment-one that can't easily be reversed. The most critical commitments have to do with the interfaces to the other parts of the chip and the software running on the microprocessor core. And here's where the basic problem lies.
Currently, designing the hardware/software interfaces is an increasingly complex, lengthy manual task. The possible hardware/software information exchanges include software writing to hardware configuration registers, software reading status and counter registers, and the hardware notifying the software about events by means of interrupts. All of this must be done as a foundation to see whether the right processor is being employed.
With the right tools, the whole process is vastly simplified. To make design exploration a practical reality, CoWare's N2C slashes design iteration time by enabling designers to quickly model a new version of a system, simulate it and then analyze the results. Since the hardware can be designed at a high level of abstraction, simulation and modeling are orders of magnitude faster. If a design assumption requires further investigation, an incremental design flow enables the relevant portion of the design to be implemented in more detail and tested in the context of the complete system.
CoWare N2C employs interface synthesis, a design technology that automates the process of connecting the different system hardware modules and interfacing them to the software. Interface synthesis also enhances intellectual property (IP) reuse by enabling designers to quickly plug-and-play different IP components. To simplify analysis, CoWare N2C provides high-level views that enable designers to understand complex system behavior at a glance. That eliminates the need to painstakingly infer overall system behavior by studying registers or waveforms.
Interface synthesis automatically implements the appropriate interface logic or software between system functions. The synthesized components include address decoding, interrupt priority encoding, arbitration units, memory-mapped registers, program and data memory, interrupt service routines, boot code and methods to access memory- mapped registers.
Automating this tedious and error-prone process frees the designer to focus on more value-added design. The designer doesn't have to spend weeks pouring through 500-page manuals that describe in English all of the features of the interface. Automating also ensures quality in interface design. And it helps designers examine new SoC design variants created by choosing a different hardware/software partition or IP model.
Interface synthesis simplifies the process of assessing and selecting the optimal intellectual property for an application. Designers can introduce new IP components without needing to handcraft the interface logic required to build a new simulation model of the entire system.
With interface synthesis, the interface between the IP block and the target processor or system bus can be designed without any detailed knowledge of the processor or bus specification, protocols, timing diagrams, memory map and interrupt vectors. Instead, the designer specifies how the IP block interfaces to a much more abstract virtual bus. Once the designer has selected a specific bus protocol, interface synthesis automatically generates the correct interface logic between the target processor/bus and the IP block.
CoWare Aware IP
Only one IP block needs to be designed and maintained to interface to many different processor and bus targets. This considerably simplifies design, documentation, delivery and support of IP blocks. IP designed to interface with the virtual bus is known as CoWare Aware IP. Pre-existing IP blocks can also be made "CoWare Aware" by capturing them for use in CoWare N2C with a simple wrapper.
A further advantage of the CoWare IP reuse methodology is that C or C++ representations are maintained for all IP blocks in addition to more hardware-specific representations. This facilitates moving specific functions across the hardware-software partition. Such functions typically move from hardware to software in subsequent product generations and from software to hardware in derivative products within a generation.
How do you make these important design trade-offs? You need tools that provide a rich graphical analysis environment with a point-and-click interface that lets you set probes at any point in a system's hardware or software modules and view analysis data. You need to be able to perform custom configuration or post-processing using a scripting language, such as Tcl/Tk.
Most of all, you need a tool that provides a variety of high-level analysis views. Gantt charts are useful to plot system response and temporal relationships between systems components. Bar charts and graphs help illustrate code hotspots, processor loading, and bus and memory performance issues, such as the number or frequency of bus contentions and retries, cache hits and misses, and paging behavior. And you need system-level simulation that covers all system component and bus activity, providing accurate statistics on switching activity to help estimate power consumption, since CMOS components consume the most power when switching states.
Once an initial partition between hardware and software is selected, a good system-level design tool like CoWare N2C can compile and link the software functions to execute on the instruction-set simulator for the chosen processor. Co-simulation is possible with any level of hardware abstraction, whether untimed C, cycle-accurate C, or register transfer-level hardware description language (HDL). As a result, a hardware virtual prototype is available as soon as a partition is made.
The virtual prototype enables the software and hardware teams to work in tandem through the complete project cycle rather than having to wait for an actual hardware implementation. A further advantage is that the virtual prototype provides much more debugging visibility than the actual SoC itself. As a result, problems can be debugged much more quickly, further shortening development.
A successful co-design environment demands the integration of many disparate components. From a software perspective, it may be necessary to integrate the instruction-set simulator, the software development tools, and a real-time operating system. For hardware development, integration of the local and system bus models, memory architecture, IP cores, and the HDL simulator of choice may all be required.
The old way to design an SoC is broken. It takes too long, makes a design that's too difficult to change, and often makes companies miss important market windows. Moving up to C-based design has been widely promoted as a way to speed the design process. However, just moving up to C is not enough.
Designers must move up to employ tools that speed them through the design process. By employing system-level design tools that use capabilities such as graphical analysis, interface synthesis, and system-level simulation, designers can reduce overall platform-based design time as STMicroelectronics did-from 24 months to six months. And they can cut the time required for a derivative platform from 10 weeks to between two and three weeks.
New Platform-Based Design Capabilities Expand CoWare's Proven Tools and Methods to Speed New and Derivative Products to Market
Provides fastest time-to-volume production for platform developers
SANTA CLARA, Calif. - August 21, 2000 - CoWare™, Inc., the leading provider of system-level design tools, has added new platform-based design capabilities to its CoWare N2C™ design system. The new capabilities include improved creation of virtual platforms, enhanced Interface Synthesis for multiple processor platforms, and easier integration of the system software with the platform.
"For the first time, platform-based design can be done at the system level, incorporating both hardware and software," stated CoWare President and CEO Guido Arnout. "CoWare's customers are leading the way in establishing platform-based design as the prevalent methodology for creation and use of core-based architectures that can be rapidly extended and customized for a range of applications. This allows some degree of stability to be brought to the system-on-a-chip (SoC) design process, while retaining the flexibility necessary to meet demand for new and derivative products."
Philippe Geyres, Corporate Vice President and General Manager of ST's Consumer and Microcontroller Groups, said, "ST is extensively using CoWare tools for the development and verification of its Product Platforms for Digital Consumer. It is also using them to enable its customers to start their system development before the availability of final silicon products. CoWare helps ST cut the time to volume of its system-on-a-chip for Digital Consumer, a segment where ST is the established leader."
The Virtual Platform - Taking Virtual Prototypes to the Next Level
CoWare N2C virtual prototypes give software designers an early accurate model of the hardware to develop and test their software, so they don't have to wait for the hardware prototype to start software development. The availability of a hardware prototype is problematic at best in an SoC design flow.
Platform-based design takes the concept of a virtual prototype a step further. Now, using CoWare N2C, designers can create a system-level platform that can be rapidly customized for a range of applications. First, the platform creator builds a base system around core intellectual property (IP) including CPUs, DSPs, memories, buses and peripherals. Usually, the base platform is developed from knowledge of the application's requirements or architectural specifications from the system-house customer, at a very early stage before the functional system specification is complete. Performance of the platform can be evaluated using CoWare N2C's advanced analysis capabilities.
New Hardware/Hardware Interface Synthesis
Then this base platform can be delivered to a system designer, who adds system IP to the platform by developing software and/or by adding extra hardware blocks to the system (using the new hardware/hardware Interface Synthesis capability). As more features are added, core IP blocks or application-specific peripherals can easily be swapped in and out using CoWare N2C's Interface Synthesis capabilities to generate all the necessary communication and glue logic. Synthesized components can include address decoding, interrupt priority encoding, arbitration units, memory mapped registers, program and data memory and controllers, interrupt service routines, boot code, and methods to access memory mapped registers. The result is a 'plug and play' method enabling the rapid creation of many derivatives.
Interface Synthesis for Multi-Processor Platforms
Often, designers want to combine multiple CPUs and DSPs in the same design. CoWare N2C has long allowed designers to model and simulate these multi-processor SoC designs. However, only one processor was available as a target for partitioning the system specification and hardware-software Interface Synthesis. Now, CoWare N2C will allow system functionality to be partitioned between hardware and software for multiple processors. Interface Synthesis will create the hardware-software communication and glue logic for each processor sub-system.
Integration of System Software with the Platform
In a platform-based design flow, the hardware-software partition may be largely pre-defined and the remaining design task is to integrate the system software onto the platform as easily as possible. CoWare's Interface Synthesis capabilities automatically generate the software interfaces to the hardware. Now CoWare has added a capability to automatically create a clear, unambiguous hardware programming interface to the platform. This interface consists of software files detailing the platform's memory map and software drivers, and automated assistance to build the software image and compile it onto the platform.
Pricing and Availability
These new capabilities are currently in beta testing and will be phased into CoWare N2C, for shipment by the end of the year, at no extra charge.
About CoWare
CoWare, Inc., provides tools and methodologies that help engineering teams cut their system-on-a-chip design times in half. CoWare N2C' provides an efficient means to capture, analyze, and implement a system specification, with parallel development by hardware and software teams. In addition, CoWare N2C greatly enhances IP re-use and selection, further reducing design time. The CoWare N2C software is employed by major systems and semiconductor companies including Alcatel, Fujitsu, Mitsubishi, Motorola, Nokia, Sony and STMicroelectronics. CoWare is headquartered in Santa Clara, Calif. USA and employs over 100 people. For more information, visit www.CoWare.com. |
