NEC narrows gate length below 0.10 micron
By Anthony Cataldo, EE Times
Oct 31, 2000 (2:58 PM)
URL: eetimes.com
TOKYO — NEC Corp. has developed a 0.13-micron generation process technology that uses a transistor gate measuring less than 0.10 micron, a length many semiconductor makers consider a technological milestone as CMOS transistors become harder to scale. Besides expected improvements in transistor speed over the 0.13-micron gate-length transistors NEC announced about a year ago, the UX5 process covers some new ground and makes up for some deficiencies of the company's previous UX4 process. These include the use of a dual-damascene, all-copper metal interconnect as well as the reintroduction of embedded DRAM. Moreover, NEC has included an optional low-leakage current library, and has promised to later introduce new ways to keep power consumption to a minimum.
Though about a year from being ready for volume production, NEC claims it has produced stable test chips on the new process and said it will release test libraries for performance verification in November. If all goes as planned, the company will start taking orders for designs in UX5 next May and ship samples by next August. Volume production is slated for November 2001.
Distinct libraries
NEC is positioning UX5 for customers making high-speed communications and graphics gear, digital consumer electronics or low-power mobile terminals. There will be separate libraries for these three areas.
The high speed CB-130H version of the process uses transistors with 0.095-micron gate length, a measure of the top electrode which traverses the source and drain, and boasts a transistor delay of 9.5 picoseconds. With a 1.2-volt supply voltage, NEC expects it can achieve clock frequencies between 350 MHz and 1 GHz, the company said.
NEC will also provide the same narrow gate-length transistor for devices used in consumer electronics, where integration and small die size carry great weight. With the CB-130M library, NEC claims it can integrate up to 62 million gates in a single device, or 1.9 times more than with UX4, while reaching frequencies up to 350 MHz.
For mobile devices, NEC has fashioned a low power process called the CB-130L that features a less-aggressive 0.13-micron gate length but has a voltage range that can be scaled from 1.2-to-0.9 volts. Reaching frequencies of up to 100 MHz, the transistors can consume 5 nanowatts for each MHz per gate, according to the company.
A new feature of NEC's UX5 process is its use of copper wiring, up to nine layers in all, as the standard wiring method. Previously, NEC did not have the dual-damascene process technology that some consider necessary for integrating copper, and the company only offered copper as an option to aluminum, which is 40 more resistive than copper. NEC now said it can do dual damascene, and will offer copper as a way to offer thinner wires at every metal layer.
Another development that paved the way for copper is the introduction of a low-k (k = 2.9), ladder-oxide inter-dielectric material for UX5. Shifting from silicon dioxide to new low-k materials is considered a must for 0.10-micron generation devices that employ copper, and many companies are still struggling to incorporate them as the 0.13-micron node comes on-stream. With the copper and low-k combination, NEC said it can reduce wiring pitch by 30 percent and coupling capacity by 15 percent.
"IBM and TSMC also use advanced 0.13-micron with dual-damascene [copper interconnect] and low-k, so we're in a similar position," said Yoshihiro Mabuchi, manager of NEC's device development department.
Though NEC claims an early lead in breaking the 0.10-micron "barrier," competitors have already made similar announcements. IBM Microelectronics earlier this year said it had developed a 0.11-micron (drawn), 0.08-micron (L-effective) process that the company said will move into high volume by the first half of 2001. And last September, Taiwan Semiconductor Manufacturing Co. (TSMC) announced that it would tape out first silicon based on its 0.13-micron process with a 0.08-micron gate length by late this year.
While gate length is an important measure of device performance, it's one of several factors that determine overall device speed. These include oxide thickness and clocking circuit design.
"The transistors are high performance, but that alone is not enough," Mabuchi said. "You also have to look at the design to achieve 1 GHz, such as the PLL and clocking."
Embedded DRAM reversal
Another is memory performance. Reversing a position it held until earlier this year, NEC has acknowledged the need to include embedded DRAM into devices that need big and dense memory configurations, such as graphics chips. In its previous UX4 process, the company had opted to not offer embedded DRAM as a standard macro due to high cost and weak customer demand. Instead, the company developed a four-transistor cell SRAMs, which provide high speed with a cell size 40 percent smaller than a standard six-transistor cell SRAM.
With UX5, NEC will offer both four-transistor SRAM cells as well as embedded DRAM. The company said it can provide up to 256-Mbits of embedded DRAM on a die. With a cell size of 1.42 micron2, the 4-T SRAM offers a density of up to 16 Mbits per die, NEC said.
"4-T SRAM is smaller than 6-T SRAM, but its still four times bigger than DRAM," Mabuchi said. "And we have a solution for reducing the cost of embedded DRAM."
To address the low-power needs of mobile handsets, NEC has introduced a triple-gate oxide film process to cut standby leakage current and various transistor types that correspond to a circuit's operating frequency. NEC said these methods will reduce power consumption by 30 percent without compromising performance. With 0.9-volt power supply, for example, its possible to design devices for an MP3 player that dissipates 100 mW, the company said. NEC is also in the process of developing an automatic voltage control technology that will determine the most suitable voltage for a device depending on its operation status, such as whether its in active and standby mode.
By arming itself with low-power techniques, NEC hopes to get an early lead in providing the core technology for the so-called applications processors expected to emerge for 3G phones. "Wideband CDMA is a very heavy spec," Mabuchi said. "Not only will it require high density but also low leakage."
To address design cycle times, NEC said it is providing both hierarchical design for chips with clock frequencies higher than 500 MHz as well as timing closure design. Using a mixture of its own tools and those from outside EDA vendors, the company said it has tools to tackle problems related to signal integrity, crosstalk, and electromigration, for example. It also has its own 3-D RC extraction tool along with several verification tools.
The company's intellectual property (IP) library will target the communications, graphics, mobile and digital home electronics segments. The library includes a network controller, ATM, Ethernet, xDSL, Direct Rambus ASIC cell, a graphics accelerator, NTSC/PAL encoder, DSP, PCI controller, USB, IEEE1394, MPEG-2 codec, JPEG, and modem functions. Other generic IP will be made available, including analog and digital PLLs, UART, register file, JTAG, FIFO, CAM, ROM, A/D and D/A converter functions, the company said.
NEC also will provide internally-developed V850E and VRx CPUs, though Mabuchi said he believes NEC will need to license the ARM9 core to address the market for mobile terminals.
The company will offer devices in a number of BGA, QFP and CSP packages, NEC said. |
