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To: Tenchusatsu who wrote (54091)9/19/2000 5:42:29 PM
From: Scumbria  Read Replies (2) | Respond to of 93625
 
Ten,

You'll change your tune once thread-level parallism starts hitting microprocessors.

We already have thread level parallelism in SMP systems. Each processor has it's own caches, and as a result we do not experience thrashing.

The more CPUs and processes/threads the more DRAM bandwidth will be required. That is why everyone is planning on using DDR for servers (except Merced.)

Scumbria


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