PMC-Sierra Announces Industry's First Dual Port Gigabit Ethernet Chip With POS-PHY Level 3 Interface
BURNABY, British Columbia--(BUSINESS WIRE)--Oct. 2, 2000-- S/UNI-2xGE Solution Brings Carrier-Class Ethernet Performance to IP Core/Edge Routers, Multi-Service Platforms and Optical Networking Products
PMC-Sierra (Nasdaq:PMCS - news) today announced the PM3386 S/UNI-2xGE dual port Gigabit Ethernet transceiver, the industry's first integrated dual Serializer/Deserializer (SERDES) and Gigabit Media Access Control (MAC) controller with the industry standard POS-PHY Level 3 system interface.
The high density S/UNI-2xGE connects directly to optical modules, offers a standard Gigabit Media Independent Interface (GMII) and operates at low power levels. By leveraging the POS-PHY Level 3 interface, the S/UNI-2xGE enables the development of Gigabit Ethernet line cards used in carrier class networking equipment. The new chip gives system developers substantial design flexibility, speeds time-to-market, and reduces the overall cost of developing Internet Protocol core and edge routers, multi-service switching platforms (MSSPs), and optical networking products.
``With Gigabit Ethernet rapidly gaining momentum as a carrier-class transport option, Internet and optical equipment designers are demanding devices that provide substantially greater port densities with low power,'' says Stuart Robinson, product marketing manager of PMC-Sierra's Optical Networking Division. ``By adding the industry's first dual port Gigabit Ethernet controller with POS-PHY Level 3 to our product portfolio, S/UNI-2xGE joins the broadest array of POS-PHY Level 3 products available.''
Low-Power, High-Speed Design Replaces Up to Six Chips
The small 27 mm x 27 mm S/UNI-2xGE chip is implemented entirely in mainstream 0.18 micron 3.3 / 1.8 volt CMOS technology, provides reduced power consumption and simplified silicon integration. Its power consumption is less than 2 watts/port, which offers up to a 60% power savings over low density Gigabit Ethernet implementations that uses discrete SERDES, Gigabit Ethernet MAC and FPGA devices. With all of these features on one chip, the S/UNI-2xGE device replaces up to six chips (see figure 1).
Gigabit Ethernet, SONET and WANs
Scalable from 1 Mbit/s to 10 Gbit/s, Ethernet is a pervasive link-layer protocol that can be easily and cost-effectively integrated into Local Area Network (LAN), Metropolitan Area Network (MAN), and Wide Area Network (WAN) topologies. To facilitate Gigabit Ethernet in Wide Area Networks, carriers and Internet Service Providers (ISPs) are beginning to implement Gigabit Ethernet over SONET/SDH optical networks.
The S/UNI 2xGE device provides an expedient way to integrate Gigabit Ethernet into multi-service architectures supporting Asynchronous Transfer Mode (ATM), Frame Relay (FR), Internet Protocol (IP), and Gigabit Ethernet (GE) traffic at 51 Mbits/s up to 2.5 Gbit/s (OC-48) line rates. With the integration of the POS-PHY Level 3 interface the S/UNI 2xGE does not require glue logic to connect to higher layer devices.
``Today, carriers and ISPs require Gigabit Ethernet technology to deploy Metro Point-of-Presence (POP) architectures because of its high speed, low cost and scalability,'' says Steve Perna, vice-president and general manager of PMC-Sierra's Optical Networking Division. ``In order to support exploding bandwidth requirements of metro optical networks, carriers and ISPs are relentless in demanding higher densities of Gigabit Ethernet and emerging 10 Gigabit Ethernet solutions.''
POS-PHY Level 3: An Industry Standard for Multi-Service System Interfaces
The POS-PHY Level 3 system interface was developed by the SATURN® Development Group in December 1998, and is publicly available at pmc-sierra.com. This interface specification, in balloting at the Optical Internetworking Forum and recently ratified by the ATM Forum, provides an industry-wide standard for multi-service system interfaces. POS-PHY Level 3 is the industry standard for 2.5 Gbit/s OC-48 and multi-channel 622-Mbit/s OC-12 transmission rates required by the new generation of super routers and layer 3 switches for multi-service voice and data networks. An interface based on this standard is flexible enough to support not only high-speed Packet-over-SONET (POS) Internet traffic, but Gigabit Ethernet and Asynchronous Transfer Mode (ATM) applications as well.
Bandwidth Requirements Driving Next Generation 10Gbit/s Interfaces
``We believe that 10 Gigabit solutions will closely follow the current Gigabit Ethernet solutions. POS-PHY Level 4, the proposed 10 Gigabit-per-second bus interface, provides an excellent method for the next generation routers to support 10 Gigabit-per-second Packet over SONET, ATM and soon 10 Gigabit Ethernet,'' says Tom Alexander, PMC-Sierra's principal engineer (and editor of the IEEE P802.3ae 10 Gigabit Ethernet WAN PHY standard and member of 10GE Alliance).
Information about the POS-PHY Level 4 system interface is publicly available at pmc-sierra.com. This interface specification, in balloting at the Optical Internetworking Forum and the ATM Forum, provides an industry-wide standard for 10 Gbit/s multi-service system interfaces. An interface based on this standard is flexible enough to support not only high-speed POS Internet traffic, but Gigabit Ethernet and ATM applications as well.
Pricing, Availability and Customer Support
The S/UNI-2xGE is packaged in a 27 mm by 27 mm, 352 UBGA package. It is priced at $259 in volume quantities, with samples available in November 2000. A comprehensive support package including reference designs, software drivers, application notes, and bus functional models will simplify design and reduce time to market. To access the reference design, Ethernet over SONET application note, and software drivers, go pmc-sierra.com. For more information about the bus functional model, email apps@pmc-sierra.com.
Ibexx |
