Patents for RMBS granted in 2000
UW - I do not have time to research this but you gotta love it - posted on Yahoo, by: watali_2000 9/23/00 4:34 pm
Msg: 163776 of 163776
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DATE
ID No.
DESCRIPTION
19-SEP-00 6,122,688 6,122,688-Protocol for communication with dynamic memory
19-SEP-00 6,122,208 6,122,208-Circuit and method for column redundancy for high bandwidth memories
19-SEP-00 6,122,189 6,122,189-Data packet with embedded mask
29-AUG-00 6,111,445 6,111,445-Phase interpolator with noise immunity
23-AUG-00 6,107,847 6,107,847-Zero power reset circuit for low voltage CMOS circuits
08-AUG-00 6,101,152 6,101,152-Method of operating a synchronous memory device
25-JUL-00 6,094,075 6,094,075-Current control technique
19-JUL-00 RE36,781 RE36,781-Differential comparator for amplifying small swing signals to a full swing output
05-JUL-00 6,085,284 6,085,284-Method of operating a memory device having a variable data output length and an identification register
13-JUN-00 6,075,743 6,075,743-Method and apparatus for sharing sense amplifiers between memory banks
13-JUN-00 6,075,730 6,075,730-High performance cost optimized memory with delayed memory writes
13-JUN-00 6,075,744 6,075,744-Dram core refresh with reduced spike current
30-MAY-00 6,070,222 6,070,222-Synchronous memory device having identification register
23-MAY-00 6,067,594 6,067,594-High frequency bus system
23-MAY-00 6,067,592 6,067,592-System having a synchronous memory device
11-APR-00 6,049,846 6,049,846-Integrated circuit having memory which synchronously samples information with respect to external clock signals
04-APR-00 6,047,346 6,047,346-System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers
28-MAR-00 6,044,426 6,044,426-Memory system having memory devices each including a programmable internal register
14-MAR-00 6,038,195 6,038,195-Synchronous memory device having a delay time register and method of operating same
07-MAR-00 6,035,369 6,035,369-Method and apparatus for providing a memory with write enable information
07-MAR-00 6,035,365 6,035,365-Dual clocked synchronous memory device having a delay time register and method of operating same
07-MAR-00 6,034,918 6,034,918-Method of operating a memory having a variable data output length and a programmable register
29-FEB-00 6,032,215 6,032,215-Synchronous memory device utilizing two external clocks
29-FEB-00 6,032,214 6,032,214-Method of operating a synchronous memory device having a variable data output length
19-FEB-00 6,021,076 6,021,076-Apparatus and method for thermal regulation in memory subsystems |
