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To: Tenchusatsu who wrote (111379)	9/30/2000 12:47:11 AM
From: Joe NYC	Respond to of 186894

Tench, <Remember when Intel touted MMX? That has turned out to be a yawner at best.> A yawner that AMD soon implemented in their CPUs. Remember when AMD touted 3DNow? That has turned out to be a real yawner, so much so that AMD now has to support SSE in their upcoming Sledgehammer. Just because AMD implements something for marketing reason doesn't mean that the technology is sound. In my opinion, a complete set / superset of FPU will start to get interesting. I guess SSE2 (in Willamette) may be it. If it is, it will be a first non-yawner as far as I am concerned. What would be needed is a few years of stability after that so that a new level is established, and some software actually gets written to use this instruction set. I think SSE was psychologically a step back. It's not a complete set, just more fiddling with more instructions, and the perception is that it is all marketing, and as a result, nobody cares (except the writers of the Intel C++ spec compiler). I hope SSE2 doesn't disappoint the way MMX/3Dnow/SSE did. Joe