Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Speedfam [SFAM] Lovers Unite ! -- Ignore unavailable to you. Want to Upgrade?

To: Ian@SI who wrote (3614)	9/26/2000 7:21:40 PM
From: SemiBull	Respond to of 3736

"It may have something to do with the switchover to Momentum." That is my understanding....but I suppose we should know more in the next 10Q, followed by next Q's results. SemiBull

To: Ian@SI who wrote (3614)	10/21/2000 10:20:45 AM
From: Proud_Infidel	Respond to of 3736

CMP may end up getting replaced by 'electropolishing' in copper processes A key problem in finding a low-k dielectric insulator for copper interconnects has been to find one that can hold up under the stress and strain of chemical mechanical polishing (CMP). Many insulating materials with lower dielectric-constant ratings can't meet the mechanical-strength requirements for CMP, which is used to flatten layers in interconnects and remove excess amounts of copper from vias and trenches. But help may be on the way. ACM Research, a Silicon Valley startup, has developed new current-controlled electroplating and electropolishing technologies that it claims "will dramatically ease" processing steps for next-generation copper and low-k dielectrics on ICs. "Our electropolishing system is 'stress free polishing,'" claims ACM's CEO, David Wang. These processes and the new tools to go with them use electrical current to control locally the deposition of copper, plating steps, removal of metal, and polishing sequences. The novel electropolishing process and tool is said to be capable of removing materials at the atomic layer down to 80 angstroms. Switching from CMP to these electropolishing techniques for planarization in dual damascene copper processes opens up a wide range of choices for low-k dielectric materials that couldn't cut it before because they couldn't withstand the stress of CMP. Now, softer dielectric films such as spin-on, porous Xerogel materials have become viable candidates for integration in damascene processes with copper. These porous films can be "tunable" and have low-k dielectric ratings less than 1.8 vs. above 3 for many of the current low-k insulators being used in prototype copper processes. Other companies also are pursuing alternatives to CMP. If the new technology catches on, it could threaten a huge wafer tool segment that is expected to top $1.2 billion in sales by 2003, according to VLSI Research. "There may not be a need for copper CMP," Wang adds. He believes his company's patented concepts also will extend the use of copper electroplating to the 0.035-micron technology node, which is still expected to be in use more than a decade from now. The cost of his alternative to CMP will run less than $2 per wafer vs. $4-to-5 with CMP tools, Wang claims.