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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: sylvester80 who wrote (55529)	9/27/2000 4:19:56 PM
From: Bilow	Read Replies (2) \| Respond to of 93625

Hi sylvester80; About the pincount required to implement another RSL channel on a RIMM. My other points are too technical to realistically discuss here. Currently, a RIMM has 184 pins. Look on page 2 of this document to see them listed in full, along with their relative positions: usa.samsungsemi.com The following pins will have to be duplicated for a dual width RIMM: LDQA[8:0] 9 RSL data bus lines RDQA[8:0] 9 RSL data bus lines LDQB[8:0] 9 RSL data bus lines RDQB[8:0] 9 RSL data bus lines LROW[2:0] 3 RSL address bus lines RROW[2:0] 3 RSL address bus lines LCOL[4:0] 5 RSL address bus lines RCOL[4:0] 5 RSL address bus lines LCFM/N 2 RSL clock lines RCFM/N 2 RSL clock lines LCTM/N 2 RSL clock lines RCTM/N 2 RSL clock lines -- Total: 60 Maybe the following have to be duplicated: LSCK 1 high speed CMOS serial clock RSCK 1 high speed CMOS serial clock SIN 1 high speed CMOS serial data SOUT 1 high speed CMOS serial data - Total: 4 In addition, all of the above lines currently have a ground pin (note no power pins) separating them from their neighbors on either side of the module. This is done to prevent crosstalk &c. The motherboards, by the way are also routed with ground traces between RSL signal lines. Adding these pins to the module bumps the trace count up by another 60/64 (maybe a few less because of getting rid of some NCs &c., but this is within a dozen of the correct count). The total number of pins required to support a second RSL channel in a RIMM: about 115 or so. This is probably about 100 more than the 16 a naive guess would have given... Since a RIMM currently has 184 pins, the new RIMMs will need something like 300 pins. This is the meaning of my statement: "It increases the pincount of the RIMM by quite a large amount." -- Carl Notes: (1) Address / control / clock lines have to be duplicated because time of flight for these lines must match the time of flight for the data bus. If the data bus goes to fewer chips, and is consequently faster, than so to must the address bus. The only way to compensate for a connection to a chip is with a connection to a chip. Consequently, the address bus must connect to the same number of chips as the data bus. If the address bus connects to twice as many chips as the data bus, then the data bus will be proportionately faster, and the proportion will depend on the particular characteristics of the RDRAM chips used. Thus the delay cannot be compensated by adding extra signal length in the data bus wires - you cannot predict precisely what the characteristics of the RDRAM pins will be. This is part of the matching principle that Rambus uses to get so closed to the edge on their timing specs. Every signal on the RSL bus has to see exactly the same thing in order for the relative delays between signals to be (close enough to) zero. (2) There is a timing relationship between the LSCK, RSCK, SIN, and SOUT signals and the RSL signals. They can't be allowed to get too far out of whack because orders to change driver current are regularly going out to RDRAM, even while the system is in use.