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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Proud_Infidel who wrote (37733)	10/3/2000 2:11:55 PM
From: Proud_Infidel	Respond to of 70976

Philips, IMEC aim to accelerate 0.10-micron CMOS by a year or two By J. Robert Lineback Semiconductor Business News (10/03/00, 01:26:38 PM EDT) LEUVEN, Belgium -- Europe's IMEC independent research group here today announced a technology acceleration program with Philips Semiconductors to make 0.10-micron CMOS processes available for chip production one-to-two years ahead of other industry roadmaps. The alliance expands upon existing collaboration between IMEC and the Dutch electronics giant, which are also working together on 0.10-micron (100-nanometer) processes as part of the European Union's Hundred Nanometer CMOS Technology (HUNT) project. The new program aims to accelerate development of a 100-mm CMOS technology using a "scaled-down" version of planar CMOS processes, such as those created for the 0.13-micron [130-nm] node, said officials during a press briefing prior to IMEC's annual research review in Leuven this week. The new development program intends to demonstrate a fully integrated 0.10-micron process, with copper metal and low-k dielectrics for interconnects, in the fourth quarter of 2002. The team expects to release the 100-nm technology for use in 200-mm wafer fabs no later than early 2003, said Herman Maes, vice president of silicon technology and device integration at IMEC [Inter-universities Microelectronics Center]. IMEC officials said the target for introducing the 0.10-micron CMOS is ahead of the current 2003-2004 timeframe identified in last year's International Technology Roadmap for Semiconductors (ITRS), published by the Semiconductor Industry Association (SIA). The SIA's 2000 update to technology roadmap is expected to also pull up the targets for 0.10-micron CMOS when the new document is finished within the next three months, but milestones are still be adjusted by committees. Philips and IMEC said they plan to demonstrate the initial integrated front-end of line (FEOL) process for 0.10-micron transistors during the fourth quarter of 2001. This demonstration technology will also include a three-layer copper interconnect module using "medium-level" low-k dielectrics and relaxed 0.13-micron design rules for the back-end of line (BOEL) process steps. A parallel effort is also underway in the development program to investigate back-up solutions for 70-nm (0.07-micron) and below technology nodes. The joint-development program will cover all process steps for 0.10-micron drawn feature size ICs (0.07-0.08-micron L-effective gate lengths), said IMEC's Maes. These process steps cover lithography, etching, cleaning, new materials (for both low- and high-k dielectrics), and copper deposition. Shallow-trench isolation, gate stack, ultra-shallow junctions, silicides, and back-end-of-line copper/low-k modules will be integrated into the process, said IMEC. The research will be conducted in IMEC's facilities and use 193-nm lithography tools.