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To: Joseph Pareti who wrote (112826)10/9/2000 1:15:29 PM
From: Tenchusatsu  Read Replies (1) | Respond to of 186894
 
Joseph, <Out-of-order processors (such as Pentium, PA-RISC, 21264 and higher) can mask latency penalties
from memory accesses by issuing load instructions in advance (instructions ordering rearranged on the fly, this cannot be accomplished by ILP).>

In IA-64, this is covered by speculation. I can see some cases where dynamic instruction reordering might be better than static reordering, but not in this case.

Tenchusatsu


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