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To: Joe NYC who wrote (13344)	10/12/2000 10:21:25 AM
From: rsi_boy	Respond to of 275872

Here's my thoughts on the Mustang core. I took a few mpu architecture courses back in the day, but the prof only got as far as the 486 so you'll have to help me out... Yes Jozef, L2 bus to 256 bit width would be fantastic -- does anyone know how difficult this would be to implement? What are the trade-offs? I'm a bit worried Athlon microarchitecture is entirely predicated on 64-bit everything. What are the die size implications of going to 2 56? Additional bus lines shouldn't be a big deal since they're on chip, would tag RAM need to be substantially larger/slower - or does tag RAM only change with associativity? Hey there's a thought, will associativity change? Maybe less associative with larger caches, or conversely larger associativity (ala Culeron vs. coppermine). I really don't think L2 latency is going to change. Two cycle seems to short for such large sizes and frequencies. We should start a poll on mustangs IPC. What will the core enhancements be? Here's my guesses is in order of plausibility: 1. Lower voltage/power 2. Tweaked layout, reduced die size 3. Minor core enhancements (ie: CTX core of K6 leading to 2-5% bonus IPC) 4. Increased latencies or lengthened pipeline reducing IPC but boosting frequency 5. Wider L2 cache bus 6. Reduced L2 latency 7. Jerry's engraved image right in the middle, one micron tall tom.