Article post:
Server MPUs jockey with Itanium
RELATED SYMBOLS: (SSNLF)(AMD)(INTC)(SSNJY)(SUNW)(IBM)
Oct. 13, 2000 (Electronic Engineering Times - CMP via COMTEX) -- San Jose,
Calif. - Though notably absent from the Microprocessor Forum session on servers
and workstations, Intel Corp.'s legend loomed large over last Tuesday's
gathering.
Speaking to a packed room, Kevin Krewell, senior analyst for MicroDesign
Resources, outlined the current server market and described how Intel's planned
Itanium chip will alter its landscape, which has grown increasingly competitive
with Sun Microsystems Inc.'s recently announced UltraSparc III, and IBM's Power4
architecture.
"Intel is not the incumbent, but the challenger this time," Krewell said. "So
it'll be interesting to see how it plays out.
"With servers, continuity is an extremely important aspect, and that's where
Intel has been successful," Krewell said. "But the key thing I want to say to
them is 'execution, execution, and oh yeah, execution.' "
Sun Microsystems' UltraSparc III, though mired in delays, caused a bit of a stir
in the analyst community when announced last month, mainly due to its on-chip
DRAM controller tasked with streamlining a processor's access to memory in a
multiprocessor environment. "In the case of Sun, sure, they had a delay, but
Intel is under a smaller microscope, and getting more attention," Krewell said.
"But Sun has done extremely well in an architecture that's getting a little long
in the tooth."
Also at the session, Advanced Micro Devices Inc. announced enhancements to its
Athlon processor line, seeking to better the Athlon's performance in
multiprocessor environments. Though targeted more at the low end of the server
market, Athlon has been fitted with a large, exclusive Level 2 cache memory,
point-to-point bus transfers (to maintain bus bandwidth when scaling) and
support for 266-MHz double-date-rate memory technology. Though admittedly not as
cutting-edge as Intel, AMD said it still feels it has an advantage. "If you
compare AMD with Intel purely by numbers alone, you're going to think AMD will
get killed by Intel, but you can't just be looking at wires and clock rates
alone," said Rich Heye, vice president and general manager for AMD's Texas
Microprocessor Division. "We're able to take full advantage of our bandwidth,
and we can execute with inexpensive, reliable technology.
"Revolutions are really hard to win," Heye added. "Evolution's the way
to go."
Samsung Electronics Co. Ltd. is also looking to stay within the bounds of its
21264 Alpha MPU, adding an on-chip L2 cache to its new 21264E, which can serve
as a drop-in replacement for its predecessor. Integrating a 1.85 Mbyte 14-way
set associative on-chip L2 cache, Samsung said the processor operating at
1,250-MHz is 100 MHz faster and supports three more Gbits/second of bandwidth
than off-chip cache. "We are trying to keep the minimum design changes, we're
trying to maintain our 21264 design," said Sung Bae Park, of Samsung
Electronics.
Power4 core
Perhaps the most significant announcement of the session was from IBM, whose
Power4 architecture for high-end systems was described at last year's
Microprocessor Forum. Big Blue disclosed the core architecture and pipeline of
the new architecture at the show. Some of the Power4's highlights include
instruction-level parallelism, including speculative superscalar organization
with out-of-order execution and aggressive branch prediction. Three L2 cache
controllers, each 8-way set associative and with a separate snoop directory,
speed the Power4's cache.
The Power4's core processor technology features a superscalar design, pipelined
and structured for high frequencies, and binary compatible with prior designs.
IBM's design has a strong system focus, with bandwidth taking the front seat.
"We believe Power4 signals in a new era in server design and engages a strong
focus on the system level," said Charles Moore, distinguished engineer at IBM's
server group.
eetimes.com
By: Jerry Ascierto
Copyright 2000 CMP Media Inc. |
