SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: jcholewa who wrote (58742)10/24/2000 7:57:40 PM
From: gnuman  Read Replies (4) | Respond to of 93625
 
New from McComas. "P3+DDR Performance Analysis VIA’s Apollo Pro266 DDR Chip Set"
inqst.com

Note: Test platform used 256MB of PC2100.

Wonder when we'll see 760 tests with 266MHz FSB?



To: jcholewa who wrote (58742)10/24/2000 8:39:08 PM
From: Dan3  Respond to of 93625
 
Re: > The P2 had many firsts in new design.
As did, for instance, the Coppermine

Great summary / analysis post.

Regards,

Dan



To: jcholewa who wrote (58742)10/25/2000 10:57:31 AM
From: John Walliker  Read Replies (2) | Respond to of 93625
 
jcholewa,

This is a much larger change than merely moving the already separated cache onto a PCB instead of plopping it on top of the cpu die (as was the case with the PPro).

At the risk of being over-pedantic, the P-PRO cache chip is beside the cpu die, not on top of it.

John


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2026 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News