Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: dougSF30 who wrote (16032)	10/26/2000 1:49:40 AM
From: Joe NYC	Respond to of 275872

Doug, Regarding the synchronous bus, what are the 'transfer points' that underperform in the asynchronous case? Is it the FSB <--> DRAM interchange that ends up wasting 1/2 an FSB cycle on average in the asynch. case? That's a little bit over my head. Pete Gerasi may be able to shed some light on this. But in general, you have the Northbridge in the middle, CPU on one side (say at 100 MHz), DRAM on the other side (133 MHz). If the frequency of these buses is not equal, there has to be some buffering implemented in the Northbridge, where the data waits for the "next bus". This buffering itself may have some overhead, so even thogh you have the data, and the bus is ready, you still have to go through the buffer, shich causes you to "miss the bus". I don't know for fact that this is happening, but if you see remember how Via chipsets get slaughtered by BX, there is some empirical evidence that this may be happening. In asynchrounous case, there are just too many states of various mismatches that optimization may be difficult if not impossible. One optimization that I think Via should optimize for is if the memory bus and FSB match. 815 may have this type of optimization built in, since 815, (which can work in asynchronous mode) is almost as fast as BX. If all you want is synchronous operation, a great amount of energy can be expanded on optimization. And since there is a match in frequency on both sides of the Northbridge, the need for buffering can be greatly reduced, if not eliminated. Joe