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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: kash johal who wrote (16103)	10/26/2000 12:04:57 PM
From: kash johal	Read Replies (1) \| Respond to of 275872

Thread, Bought some AMD at $19 1/2. Like the news on 30th release. regards, Kash

To: kash johal who wrote (16103)	10/26/2000 12:28:21 PM
From: jcholewa	Read Replies (3) \| Respond to of 275872

> Mustang sure is an enigma to me. > There are rumors that AMD has added 2 more stages to the pipeline. > This would increase Mhz by 10-20%. > It would also reduce IPC by 10% or so over tbirds. > What do u think?? There are a number of advantages in the Mustang that can overcome any small branch midpredict penalty disadvantage. Mustang has hardware prefetching (as rumoured by c't, but for reasons of morality I can't really confirm or deny this) which can dramatically decrease effective memory latency, especially in orderly loops. There is also one advantage that Mustang has which I suspect you may see as a solid move in the right direction for performance and compatibility. Also, I don't think that adding two stages to the instruction pipe will take off ten percent. That seems like a lot of penalty for just a little increase in branch miss penalty. I mean, if adding two decreases performance by 10%, why is Willamette (which prolly has branch miss penalties near twenty cycles, and in fact supposedly much higher if the trace cache misses) only rumoured to be fifteen or twenty percent slower in per-clock performance?     -JC

To: kash johal who wrote (16103)	10/26/2000 2:25:43 PM
From: dale_laroy	Respond to of 275872

Although highly unlikely, this would not be unprecedented. Intel added one pipeline stage from Pentium to Pentium MMX. My guess is that AMD is achieving their higher speed bin yields just by replacing standard cell logic along critical paths by fully custom logic. Performance enhancements will probably be limited to removing the two branch targets within each Branch History Table entry limit and wider data paths between on-die cache levels. Less likely, but more likely than additional pipeline stages are: addition of SSE and support of critical word first bursts.