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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: jcholewa who wrote (16134)	10/26/2000 2:44:14 PM
From: Petz	Respond to of 275872

JC, if AMD adds anything to ISSE, they had better do it in a totally compatible way. That would be an awesome, and totally unexpected accomplishment. However, Intel's implementation of SSE2 is disappointing. See, it's essentially scalar in nature, as is Willamette's x87 and MMX implementations. They have 128 bit registers to allow 4 simultaneous 32-bit or 2 simultaneous 64-bit FLOPS, right? But, of course, the Intel FPU is too weak to do either of the above in one clock cycle, or even two clock cycles, so expanding the registers to 256 bits wouldn't buy you much on the PIII (or P4?). However, with the 256 bit interface to L2, 256 bit wide registers would have made a lot of sense, even if a 4-way 64 bit FLOP took several clock cycles to complete. In the case of AMD implementation, the FPU is twice as powerful as the PIII's, but the cache bandwidth is too low. So, I don't think extending the registers to 256 bits would buy anything on the Athlon either. 128 bits would match the Intel implementation, speed up 3D graphics operations up to 2:1 vs. Athlon and eliminate any P4 advantage from ISSE. Petz

To: jcholewa who wrote (16134)	10/26/2000 2:51:35 PM
From: dale_laroy	Read Replies (2) \| Respond to of 275872

Sorry, but with P4 pushing consumer buttons on desire for 1.0+ GHz, through Q3 2001 Intel's market share will not be limited by their own capacity, but rather by AMD's capacity. AMD will be able to run a combined total maximum of 9000 wafer starts per week beginning in Q1. Average yield per wafer, at least 210 processors. This is 1.89 million processors per week, 24.5 million processors per quarter, potential. Of course, lines have to be taken down for various things, such as maintenance and mask changes, but 14.4 million processors in Q1 would not be unobtainable. This would give AMD well over one third the total market in Q1.

To: jcholewa who wrote (16134)	10/26/2000 3:28:38 PM
From: porn_start878	Read Replies (1) \| Respond to of 275872

JC, Actually, SSE2 is without doubt a better floating-point instruction set than x87 is. Even without the advantage of SIMD, it lessens pressure on the decoder end (because you don't need to use FXCH to jumble around the stack). However, Intel's implementation of SSE2 is disappointing. See, it's essentially scalar in nature, as is Willamette's x87 and MMX implementations. If AMD implemented superscalar SSEx (and I'm not talking about like the double instruction pumping that P6 has to do for SSE) just like they have superscalar x87 and MMX, then SSE2 will become a much more attractive option to several coders that I know. Of course, caches and memory will have to get a lot better to meet requirements of eight sustained 32-bit operands per cycle (or four sustained 64-bit operands per cycle) throughput. Heck, caches and memory still need to catch up with the original Athlon's superscalar x87, which is obviously underperforming its own specs! I have no doubt SIMD FPU do way better than old x87, but who ever doubt that the Alpha CPU was better than any other x86 ones... the big issue is the compatibility. Look at the emotion engine which runs at a crappy 300MHz at throw up 10 times as much polygons than the most beefed up x86 setup. This is Intel we're talking about. The company with three times as many x86 fabs as every competitor combined. If the lowest performing Duron beats the highest performing P4XP next year (incredibly unlikely, of course), then Intel will still dominate at least three quarters of the market. By fckd I meant that they wont be able to save their asses by having a better SSE support in some benches. There are no such scenario in my mind where AMD outship Intel. But if nano-AMD succeed to outperform giga-Intel for 1-2 years, then I'll be awesomely proud of them and they should see rapid growth. Max