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To: Tony Viola who wrote (115143)10/29/2000 6:39:52 PM
From: Tenchusatsu  Respond to of 186894
 
Tony, <No ECC on the cache? That's pretty bad. IBM and HP sales people should have a field day over that one.>

I was asked that question last year at MPF 1999 by one engineer, why caches these days are getting ECC. He could understand ECC for DRAM, but not for SRAM. I guess Sun just demonstrated now what could happen if ECC is left off the cache.

You're right, IBM and HP should indeed be having a field day with that.

Tenchusatsu



To: Tony Viola who wrote (115143)10/29/2000 7:54:05 PM
From: Paul Engel  Read Replies (1) | Respond to of 186894
 
Tony - re: 'No ECC on the cache? That's pretty bad. IBM and HP sales people should have a field day over that one'

Didn't Intel make a major change on its Pentium II XEON(and subsequently all Pentium IIs and IIIs) cache memories about 3 years ago to include ECC on all the cache ?

I recollect they did this at the behest of IBM.

Paul


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