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To: sylvester80 who wrote (59350)	10/31/2000 12:39:04 PM
From: Joe NYC	Respond to of 93625

Sylvester, You are making great leaps of logic here. It was posted here and elsewhere (by Tench I believe) that all the transactions through the bus must start from it's base position. This means that the fact that the bus is DDR doesn't speed up the beginning of the transaction. All DDR FSB does is decrease the time a transaction takes to complete. The only possible improvement in latency is a reduction of time it takes to fill a cache line, but there is no improvement in time to deliver the critical word. Another thing you may be confused about is the fact that a PC has a number of components. Memory is only one of them. You have the chipset, the cpu, FSB, hard disk, hard disk interface, various caches. How do you possibly expect the performance of the system mirror improvement 100% increase of only one of the features of memory - the bandwidth? If all components (say 6) of the system improved by 100%, what would you expect to happen to overall performance? I would expect 100% increase. Based on your logic, you would expect 6300% improvement. I think you may want to read some more basics about how a PC operates before you jump to conclusions. Joe