'Fat' memories, fast logic to reign at next ISSCC
By Brian Fuller
EE Times
(11/03/00, 04:22:10 PM EDT)
SAN FRANCISCO -- Ultra-fat memories with more than a billion transistors, roaring logic devices, Bluetooth innovations and exotic genetic circuits will highlight the 48th International Solid-State Circuits Conference next February, where researchers will show off their attempts to drive digital convergence.
More than 160 papers from all regions of the world will be presented during the annual IEEE-sponsored get-together here Feb. 4-8. Keynotes will be delivered by Pat Gelsinger, chief technical officer of Intel Corp.; Kei-ichi Enoki of NTT Docomo Inc. in Tokyo; and Leon Cloetens, vice president of Alcatel Microelectronics in Zaventem, Belgium.
On the storage front, world memory leader Samsung Electronics Co. Ltd. of South Korea will claim to have broken through the flash memory density ceiling with a 1-Gbit multilevel-cell NAND device operating at 3.3 volts. The densest device in production today is 64 Mbits. Samsung's 0.15-micron CMOS design, which provides 1.6-Mbyte/second programming throughput, also lets users toggle from 2-bit-per-cell usage (multilevel cell) to 512 Mbits, or 1 bit/cell, for faster performance. The device uses shallow-trench isolation, three wells and two metal layers. It has an effective cell size of 0.14 micron2 and a chip size of 116.7 mm2.
"It's not trivially done, but you do have the choice," University of Toronto professor Kenneth C. Smith, who has written the overview for the upcoming conference, said of the toggling feature.
Samsung also fattens DRAM densities with a 4-Gbit double-data-rate SDRAM. The architecture eschews the 0.14-micron technology node used for 1-Gbit devices in favor of 0.10-micron CMOS to realize a 0.10-micron2 cell. Samsung researchers used gain-controlled pre-sensing and active calibration of bit-line reference voltages to improve sensing margins. The company said the design is the first time 4 billion transistors have been contained on a single IC.
Researchers will also turn the crank on ultra-high-end digital logic by showing off five designs that exceed GHz clock rates.
Intel will present two papers detailing its recent innovations in both the IA-32 and IA-64 segments. Attacking low-power/high-performance dilemmas for handheld applications, Intel will describe an enhancement to the IA-32 architecture that offers up to 1,000-Mips performance at 800 MHz but runs at operating voltages of 0.7 to 1.65 V.
Intel engineers also will describe a 4-GHz integer execution unit deployed in 0.18-micron CMOS. The design, which runs the ALU at twice the frequency of the rest of the processor to reduce latency, is designed to boost desktop and server speeds while retaining instruction-set compatibility.
Circuit techniques that Intel deployed in an implementation of the ARMv5TE allow power and performance to be widely adjusted for use in mobile devices. The device, to be described at the conference, is a 16.77-mm2 hard macro intended for use in system-on-chip (SoC) designs.
At the IA-64 level, Intel bumps up by 1.5 times the frequency of its current 64-bit processor in a 1.2-GHz design that exploits 3.3 Mbytes of on-die cache, organized among four separate arrays in a three-level hierarchy. The lowest levels of cache achieve a low enough access time to enable zero-penalty access for integer instructions, Intel will report.
Engineers from Compaq Computer Corp. are keeping pace on the high end with a 1.2-GHz Alpha processor that claims a 44.8-Gbyte/s chip-pin bandwidth. The design incorporates a 1.75-Mbyte L2 on-chip cache.
Sun Microsystems Inc. will describe a version of its MAJC processor, including two complete four-way-issue VLIW processors running at 500 MHz. And IBM Corp. will describe a Power4 processor running at more than 1 GHz with two four-way out-of-order-issue processors.
Law breakers
Smith noted that advances in logic speed have far outstripped recent expectations. In a single year, he noted, the maximum reported processor frequency, maximum transistor count and integrated cache-memory size have all doubled. That's faster than Moore's Law would dictate.
Those logic innovations will be complemented by a panel session in which participants wrestle with issues such as how designers will continue to drop voltages while breaking through the 100-watt power dissipation barrier and how architects will overcome the methodology hurdles to laying out multihundred-million transistor designs.
The commercial rush to build out wireless and wireline communications infrastructures will reap the benefits of other design innovations presented at ISSCC. Conexant Systems Inc. will show off a 22-milliwatt Bluetooth transceiver, and Alcatel engineers will describe the first fully integrated single-chip Bluetooth (1.0.b) system-on-chip. The Alcatel device integrates all the RF and digital components, including the radio, digital baseband processor, microprocessor and flash memory. The device is integrated in quarter-micron CMOS.
"Bluetooth seems to be becoming very real," Smith said. "That's exciting as far as the history of people doubting its potential."
The conference also will showcase the first designs to implement the new IEEE 802.11a wireless LAN standard. The ICs support data transmission at up to 54 Mbits/s, up from contemporary WLAN speeds of 11 Mbits/s.
Researchers from IMEC in Leuven, Belgium use new interpolating-equalizer architecture and programmable acquisition to cover all transmission modes and achieve high data rates. The die size is 20 mm2 in 0.18-micron CMOS and consumes 199 mW of power at 20 MHz.
Engineers from Australia's Radiata Communications will describe a design that incorporates all baseband-processing functions in the 5-GHz band. The baseband tone signal is coded orthogonal frequency-division multiplexing, modulated with binary phase-shift keying, quadrature PSK, 16-QAM (quadrature amplitude modulation) or 64-QAM.
Insatiable appetite
Wireline communications innovations continue to push the frequency envelope in a seemingly fruitless effort to sate the world's appetite for bandwidth. But this year's focus shifts to cost reduction in an application area that has had to leverage relatively expensive gallium-arsenide technologies for speed.
Newport Communication, for example, will describe an integrated Sonet OC-48 transceiver implemented in a nearly run-of-the-mill quarter-micron CMOS.
Researchers are also tackling the problems of integrated multimedia processors for applications ranging from handheld devices to set-top boxes and home servers. Broadcom Corp. will show off a universal set-top box SoC that integrates a complete digital TV transceiver, an MPEG-2 audio and video decoder, a 2-D/3-D graphics processor and an 8-MHz CPU.
The device incorporates all required analog interfaces for the multistandard receiving and transmitting function, such as QPSK and 64/256 QAM. Broadcom has implemented the design using 14.6 million transistors consuming just 3 W on a 94-mm2 die.
On the Buck Rogers front, researchers have made strides in organic electronics. Researchers from Cellicon Biotechnologies of Boston will describe biological devices for cellular control, while Yale University scientists will discuss the design and measurement of molecular-electronic switches and memories. Researchers will describe molecular random-access memory with refresh times larger than 10 minutes and genetic circuits such as a flip-flop and clock.
Smith, in the conference overview, writes that "engineered genetic applets, downloaded into living cells, may act as nano-robots for a variety of functions, such as removing toxins, repair of genetic disorders and control of synthetic organs, as well as interfacing to microelectronic circuits."
Other topics to be addressed during the paper sessions, to be held Feb. 5-7 at the downtown Marriott Hotel, will include advanced floor-plan-design methodology, strained-silicon-on-relaxed-silicon germanium device technologies and global interconnect schemes.
Gelsinger will hold forth on microprocessor-design challenges in the new millennium, discussing advances in system performance, power management and microarchitecture. Cloetens of Alcatel, whose keynote address is titled "Broadband Access: the Last Mile," will discuss new structures for analog drivers, power amps and D/A converters to achieve transmission performance at reasonable power.
Enoki of NTT Docomo will cast his net over mobile Internet technologies, such as Japan's i-Mode, which has landed 12 million subscribers in 18 months.
More information on the conference and registration can be found online at www.isscc.org/isscc/. |
