Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Alighieri who wrote (18146)	11/8/2000 12:50:25 AM
From: fyodor_	Read Replies (1) \| Respond to of 275872

Al, Why would it only hurt AMD? Well, the logic here was that Intel might be soaking up everything available. Fyodor, I am not sure I understand what you disagree with. Attenuating or leaky chrome and alternating psms are used to achieve sharper edge definition ... Ok, it's getting late for me and I can see I'm starting to become somewhat incoherent (it's 6:30am and I'm only up in order to watch the US election). I'll give it one last shot tonight ;) AMD and Intel currently employ 248nm light. Presumably using PSM and OPC, they are reaching gate sizes of down to around 100nm. Ok, I assume we agree on that bit... NumeriTech have, however, managed to squeeze out 50nm gate sizes using the same 248nm equipment by using CHROMELESS PSM. They claim that their new method is the way to go in order to get below 100nm gate sizes. AMD seem to currently be using NumeriTech technology: Almost one year ago, Motorola announced the successful fabrication of 0.1-micron feature sizes using NumeriTech's phase-shifting software and a standard 0.18-micron silicon production process. (source: electronicnews.com Considering that AMD is using Moto's process, the above would seem to apply to AMD. A bit further down in the same article: "This work looks at the application of chromeless phase-shift masks to sub-100nm gate length SOI transistor fabrication,"according to the abstract for the Fritze paper. "The double-exposure technique of Numerical Technologies is extended to the chromeless-edge case. Two masks are used in this method. The first is a darkfield mask with chromeless edges defining the minimum geometry gates and the second is a binary blockout mask, which also patterns the larger gate features." This would seem to be Moto's .13mu SOI process using 248nm litho equipment. Trying to close the circle my thoughts are moving in... Hans de Vries lists AMD's .13mu 248nm process as having 80nm Leff, while Intel's .13mu 193nm is listed as 70nm. I don't know if these numbers are 100% accurate, but AMD must be doing SOMETHING different in the OPC and/or PSM arena since they are managing to shrink the feature sizes by 20% without going to 193nm lithography equipment. And, clearly, these changes are not trivial - otherwise a) Intel and AMD would be doing it right now, b) Intel would be able to get much smaller feature sizes than the listed 70nm (remember, NumeriTech claims success at 50nm Leffs about 1 year ago). Hope this makes some amount of sense... -fyo