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To: TechieGuy-alt who wrote (18977)	11/13/2000 10:51:12 PM
From: porn_start878	Respond to of 275872

yep, but do you know why? Different process? Max

To: TechieGuy-alt who wrote (18977)	11/14/2000 12:00:20 AM
From: TechieGuy-alt	Read Replies (2) \| Respond to of 275872

Finer process. Same reason why 0.18 microns K7's operate with 1.7 volts while 0.25 microns operated with 2.2 and higher volts and 0.35 micron K6's operated with 2.7 and higher volts. Broadly that's the reason, though there is no rule connecting the "microns" with a particular voltage. Thinner gate oxides require lesser and lesser voltage for reliable operation. But I'm no "process expert". Maybe some one more experienced can comment on this (or point out if I am wrong). JMH(MMIFOW)O (<- can you figure this one out? :) TG

To: TechieGuy-alt who wrote (18977)	11/14/2000 6:43:24 AM
From: nixtox	Read Replies (1) \| Respond to of 275872

Question: how does DDR lower power consumption, as I've heard Scumbria say? IIRC Another reason is that since the transfer takes half the time and that being when the power consumed by the memory is highest (when memory chips are selected), then it should roughly divide the time of maximum power by two (the time when the memory is not selected of course would remain equal to non DDR). Hence reduced average power. Of course the power used during transfer may be a bit higher that in a regular SDRAM but not twice as much, the net result is still a power reduction. Comments anyone? Nick