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To: fyodor_ who wrote (19123)	11/14/2000 9:41:30 PM
From: Scott D.	Respond to of 275872

re: SIMD II double precision floats I have some experience with the old FPU math, but so far have only read about MMX and SIMD fpu math (I have used MMX and SIMD heavily for integer math). From reading the public documents on the Intel site, it appears that the Pentium 4 gains the ability to operate on two 64-bit (double precision) floats in parallel. For example, see the ADDPD instruction description: ADDPD-Packed Double-Precision Floating-Point Add Description Performs a SIMD add of the two packed double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the packed double-precision floating-point results in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See Figure 11-3 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1 for an illustration of a SIMD double-precision floating-point operation. Operation DEST[63-0] <-DEST[63-0] +SRC[63-0]; DEST[127-64] <-DEST[127-64] +SRC[127-64]; Opcode Instruction Description 66 0F 58 /r ADDPD xmm1, xmm2/m128 Add packed double-precision floating-point values from xmm2/m128 to xmm1.

To: fyodor_ who wrote (19123)	11/14/2000 9:42:09 PM
From: Scott D.	Read Replies (1) \| Respond to of 275872

re: SIMD II double precision floats I have some experience with the old FPU math, but so far have only read about SIMD and SIMD II fpu math (I have used MMX and SIMD heavily for integer math). From reading the public documents on the Intel site, it appears that the Pentium 4 gains the ability to operate on two 64-bit (double precision) floats in parallel. For example, see the ADDPD instruction description: ADDPD-Packed Double-Precision Floating-Point Add Description Performs a SIMD add of the two packed double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the packed double-precision floating-point results in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See Figure 11-3 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1 for an illustration of a SIMD double-precision floating-point operation. Operation DEST[63-0] <-DEST[63-0] +SRC[63-0]; DEST[127-64] <-DEST[127-64] +SRC[127-64]; Opcode Instruction Description 66 0F 58 /r ADDPD xmm1, xmm2/m128 Add packed double-precision floating-point values from xmm2/m128 to xmm1.