Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: jcholewa who wrote (19177)	11/15/2000 12:48:32 PM
From: Charles R	Read Replies (1) \| Respond to of 275872

JC, <P4 stands to benefit FAR MORE than PIII with prefetch instructions. The whole point of prefetch is that it leverages memory bandwidth to improve effective memory latency. Da-da, da-daaaaaaa! Pentium 4's platform has far better bandwidth than PIII's platform, so liberal use of prefetch won't choke up P4's memory subsystem like it would on PIII.> While there is some truth to this argument. There comes a point when prefetch helps than hurts because of thrashing in the cache. Also, I don't think PIIIs FSB133 was being saturated with prefetches. Bottom line: I do not believe the jump attributable to the FSB400/Dual-PC800 is that much. My guess is about 5% (compared to FSB133/Dual-PC800). <Add to that the fact that specfp is one of the most memory bandwidth constrained benchmarks out there (slight embellishment). Quake is a similar case, though not quite as extreme.> Again, FSB400 helps but I do not believe is the reason for the performance you see. Chuck

To: jcholewa who wrote (19177)	11/15/2000 1:45:05 PM
From: kapkan4u	Read Replies (1) \| Respond to of 275872

<P4 stands to benefit FAR MORE than PIII with prefetch instructions. The whole point of prefetch is that it leverages memory bandwidth to improve effective memory latency. Da-da, da-daaaaaaa! Pentium 4's platform has far better bandwidth than PIII's platform, so liberal use of prefetch won't choke up P4's memory subsystem like it would on PIII.> That is a theory. The reality is that P4 uses hardware prefetch and you can't even force Intel 5.0 compiler to generate software prefetch for P4. Also, all but one specfp2k benchmarks use double precision FP and the 5.0 compiler is hand tuned to recognize and vectorize the important inner loops in specfp2k by generating SSE2 instructions like addpd and mulpd. So P4 specfp2k numbers are among the most shameless Intel concoctions. Pregnant chad anyone? Kap