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To: Petz who wrote (19241)	11/15/2000 3:33:42 PM
From: fyodor_	Respond to of 275872

<Petz: The problem with P4 Rambus vs. TBird DDR is P4 is worse than TBird (even more so, Palomino) for two reasons: 1. Small D-cache causes applications to be limited by memory latency as L2 can't fill all the requests demanded of it 2. Branch mispredicts aften cause a delay proportional to memory latency rather than to clock speed Rambus systems are worse than DDR systems because of the same memory latency problems.> I did mention that the higher latency of Rambus in the P4/DDR system was something of an unknown ;). P4+DDR will show just how much this affects scaling. I had already read the scalability list you quote when I wrote my original message, but I do consider it authoritative on the subject. I'd like to see much more controlled tests, using larger differences in processor speeds and a wider range of programs (or, at least, a different range). There are so many differences in the listed systems' specs that no reasonable second order comparison can be done. First order is tough enough. -fyo