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To: jcholewa who wrote (19481)	11/17/2000 5:47:08 PM
From: peter_luc	Respond to of 275872

JC, very nice post, congratulations! Peter

To: jcholewa who wrote (19481)	11/17/2000 8:14:28 PM
From: rsi_boy	Respond to of 275872

excellent post JC. Well researched, well argued. You should circulate it more widely. I fear there's going to be a lot of media types in need of education once the hype hits the fan on Monday... T.

To: jcholewa who wrote (19481)	11/18/2000 7:38:17 AM
From: fyodor_	Respond to of 275872

<JC: For those interested, I posted a response to it.> Very nice response, JC ;) One thing that struck me as really odd in Kewney's article was that he blamed the P4s bad performance on DRDRAM: And the problem is Rambus. Intel delayed the launch of the P4 twice because the only motherboard chipset it has is the 850 design, which uses Rambus memory. And Rambus memory is fine (if costly) up to about 250 megabytes and up to about 1,000 MHz clock speed; and after that, it simply can't be made to go any faster. The problem is cache misses. If the data you want isn't on the processor, it takes too long to retrieve it from the lower levels of memory. This paragraph is just pure nonsense. He also goes on to (implicitly) say that the reason Intel delayed the i850 was either directly do to rambus or indirectly so, in that they wanted to do DDR SDRAM instead. Personally, I have no idea what the problem with the i850 chipset was that caused the delay, but I doubt it had anything to do with rambus (and it certainly wasn't Intel wishing to get a DDR platform out there). After all, they already have two rambus chipsets working just fine. -fyo