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To: Ali Chen who wrote (19844)11/20/2000 6:35:36 PM
From: fyodor_Respond to of 275872
 
<Ali: What do you see as "revolutionary" in the P-4?>

I was quoting something I read (hence the quotes) ;-)

That said...

The length of pipeline increased to absurd?

Yes. A radical deviation from normal procedures. And Intel did do an awful lot of work trying to minimize the penalty of pipeline stalls / flushes.

The "high-bandwidth" quad-pupmed bus when everyone knows that it is the bus latency that holds system performance?

I don't know that. Btw, why doesn't the Athlon support critical word forwarding?

Trace cache with yet-to-be-proven advantages in real life against well-known disadvantages?

With the risk of sounding like Paul Demone, I seriously doubt Intel would implement this fiendishly complicated trace cache setup, if slapping on 64kB 4-way L1 cache was quicker.

-fyo