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Technology Stocks : Network Appliance -- Ignore unavailable to you. Want to Upgrade?

To: Uncle Frank who wrote (5246)	11/21/2000 5:49:29 AM
From: Rich1	Respond to of 10934

Thanks....Here's an excerpt from a Gilder report over the summer: The company with by far the best PowerPoints and acoustics, however, is EZchip of Migdal Haemark in Israel, which manages to hit nearly all the paradigm buzz buttons at once with one set of 29 slides. It uses a heavily parallel and pipelined architecture with 64 programmable datapaths that it calls TOPs (task optimized processors), all integrated on a single chip. Each TOP spins one of the key network device functions, including parsing (or classifying), searching, resolving, and modifying packets. Under CEO Eli Fruchter, it promises wirespeed at 10 gigabits a second for all seven network layers—including access control, accounting, web page switching, content addressing, load balancing, service level agreement guarantees, voice over IP and video broadcasting. EZ does it Even using configurable PowerPoint substrates, these are all awesome claims. At 10 gigabit wirespeed, the time to process each packet is just 60 nanoseconds. Off-chip DRAM takes 60 nanoseconds for just one fetch. Fruchter's solution is the paradigm. Avoiding the speed of light delays necessarily entailed by off-chip memory, he uses low and slow on-chip CMOS DRAM with very wide (256 to 512 bit) buses to the processors that yield a total memory bandwidth of 500 gigabits per second. To achieve the applications layer content searching and switching, EZchip has developed five patented search algorithms that reduce by tenfold or more the number of memory fetches. Early next year, the chip will be transferred from PowerPoint to tapeout to be manufactured in 0.18 micron CMOS at "the world's leading foundry" according to Fruchter. In August, the company's 60 Israeli engineers completed the coding of the chip design in VHDL (Visic hardware design language). Although any bet on slideware may slip, the many eager candidates to design in EZchips are said to include the top networking equipment companies. EZchip seeks to usurp first generation network processors that integrate several off-the-shelf RISC (reduced instruction set computing) machines on a chip and couple them to separate co-processors. General purpose devices, RISCs cannot delve deep into packets. Other net processors use a mix of RISCs and ASICs, charging the RISC with the core processor tasks and the ASICs with specific high-speed jobs. ASICs add to the number of chip interfaces and by definition are not programmable. All first generation net processors use off-chip memory, imposing a 32- or 64-bit limit on the links—the buses—between processor and memory. Five megabytes of on-board DRAM (2 MB for the buffer and 3 MB for searching) and buses as wide as 512 bits mean EZchip can go beyond reading simple headers in network layers 2-4 and deep into the strings of text-based data in layers 5-7. Processing layers 5-7 is essential for such functions as server load-balancing and per-use accounting of web-based video or software applications. Scalable and cascadeable, EZchip's first product, the NP-1, can process eight ports of 1 gigabit Ethernet, one port of 10 gigabit Ethernet, or one port of OC-192 SONET. Samples will be available next spring, with volume shipments by summer. If you do have any opinions I would appreciate your input.