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To: Joe NYC who wrote (20078)	11/21/2000 2:57:04 PM
From: Tony Viola	Read Replies (1) \| Respond to of 275872

What do you think of 2 potential impediments to frequency scaling that Scumbria pointed to: 2 cycle latency L2 Joe, any computer or CPU chip company would kill for a 2 cycle latency L2. Do you mean a 2 cycle cycle time L1? Tony

To: Joe NYC who wrote (20078)	11/21/2000 2:59:14 PM
From: fyodor_	Respond to of 275872

<Joe: What do you think of 2 potential impediments to frequency scaling that Scumbria pointed to: 2 cycle latency L2 and double frequency ALU?> I've followed the whole 2 cycle latency debacle quite closely since its inception. While fully acknowledging that I am NOT a process or design expert, I don't think this particular aspect will prove much of an impediment. Well, perhaps I should rephrase that. I believe that IF it does become a limiting factor for P4 frequency scaling, Intel will increase the latency to 3 cycles (and maybe dual-port it or something). Additionally, I have seen some arguments (by Demone, I believe) that the 2 cycles constitute some form of effective latency and that for scaling purposes, the cache actually has a 3 cycle access latency. The double clocked ALU is another matter altogether, especially since more than the ALU itself appears to be running at the faster clock. I don't know if Intel has contingency plans if this particular aspect of the P4 becomes a problem (assuming that it isn't already). Returning to my original statement for a second... I don't think anyone actually questions whether or not the P4 has more frequency headroom than the PIII (considering that the PIII's headroom appears to be rather close to zero). -fyo