United States Patent 6,157,558 (2 of 7)
Wong Dec. 5, 2000
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Content addressable memory cell and array architectures having low transistor counts
Abstract
An SRAM-based CAM cell and CAM array architecture reduce transistor count and memory size by replacing pass transistors and search transistors of conventional SRAM-base CAM cells with a pair of transistors having gates coupled to bit lines. The two bit-line-controlled transistors in a CAM cell are between storage nodes and a word/match line for the CAM cell. The sizes of pull-up and pull-down devices in the CAM cells are selected so that grounding a storage node to a word/match line through one of the two bit-line-controlled transistors can change the bit stored in a CAM cell, but applying a voltage (near the supply voltage) from the word/match line through either of the two bit-line-controlled transistors to a storage node cannot change the bit or data stored in a CAM cell. Accordingly, a write operation grounds a selected word/match line and applies a voltage to the unselected word/match lines. A search operation charges all word/match lines and senses the word/match lines. Addition of a mask element that controls the connection of the CAM cell to the word/match line can convert a binary CAM architecture to a ternary CAM architecture. The mask element optionally includes circuitry that causes the mask element to power up in a known state. Within the ternary CAM cell, a bypass transistor can be provide to bypass the effect of the mask element and facilitate write operations or temporarily suspend local masking.
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Inventors: Wong; Sau-Ching (Hillsborough, CA).
Assignee: SanDisk Corporation (Campbell, CA).
Appl. No.: 316,499
Filed: May 21, 1999
Intl. Cl. : G11C 15/00
Current U.S. Cl.: 365/49
Field of Search: 365/49, 154, 156
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References Cited | [Referenced By]
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U.S. Patent Documents
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Primary Examiner: Phan; Trong
Attorney, Agent or Firm: Majestic, Parsons, Siebert & Hsue
35 Claims, 10 Drawing Figures |
