SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Paul Engel who wrote (20354)11/23/2000 5:33:43 PM
From: Gopher BrokeRead Replies (1) | Respond to of 275872
 
And AMD has to make these 64 bits SSE2 as will as 32 bit SSE2 instructions.

SSE2 operates on eight 128 bit registers and can load/store those registers from either floating point or general purpose registers. The bulk of the SSE2 work will have no interaction with the GP registers.

AMD will probably choose to enhance the SSE2 instruction set to support loading/storing from the full 64 bits of all x86-64 GP registers (rather than the low-order 32 bits) but that is by no means an essential change. They could equally well stick to the current SSE2 ops of loading from the legacy part of the x86-32 compatible GP registers.

The big advantage of x86-64, as I see it, is that AMD can take an evolutionary approach to the hardware in the same way as developers can evolve their software.



To: Paul Engel who wrote (20354)11/25/2000 11:40:50 PM
From: Charles RRead Replies (1) | Respond to of 275872
 
<And AMD has to make these 64 bits SSE2 as will as 32 bit SSE2 instructions. They will be busy for about a year or more. >

It is going to take a long while for SSE2 optimizations to become prevalent. AMD should do fine on on most 3D kind of benchmarks once basic SSE is implemented.