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To: Paul Engel who wrote (20620)11/27/2000 10:22:00 AM
From: fyodor_Respond to of 275872
 
<Paul: I also bought a beautiful Sony 18.1 inch flat panel display which will not arrive for a week or two as well.>

Not in an SSE-compatible manner ;)

Btw, I'm somewhat disappointed with the P4 SSE implementation. SQRT and DIV are (still) very slow and completely unpipelined. I guess this is to be expected since the FPU is largely unchanged from the P6 core. Hopefully some group somewhere in Intel-land is working on a new FPU.
When do you think we might realistically see a new FPU? I assume the .13mu shrink of P4 is too early...

I also wouldn't mind seeing a lower L1 latency for FPU data (6 cycles, as opposed to 2 for integer).

-fyo



To: Paul Engel who wrote (20620)11/27/2000 6:03:38 PM
From: Charles RRespond to of 275872
 
<The ThumperTurd already has most of SSE implemented. >

Check back when compilers generating SSE code run on Athlon.