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To: Daniel Schuh who wrote (21373)	12/2/2000 7:27:05 PM
From: Mani1	Read Replies (1) \| Respond to of 275872

Dan re <<my understanding is that all thermal and cooling stuff is temperature gradient dependent.>> Yes Re <<With current flip-chip packaging, the active area of the silicon is on the heat sink side of the package, right? So there's just not that much bulk material that the thermal energy has to go through in the first place?>> Don't think of the die as an isothermal 2D surface. Die has thickness and heat is generated in many of the layers. Also the die is not isothermal because heat is not uniformly generated throughout the die. Some parts of the die (active), generate a lot more heat than some other parts, so the die sometime acts a bit like a heat spreader. Overall there can be a case made by the benefits of a higher thermal conductivity die, but saying the junction temperature decreases 30% (based on what temperature unit?) is just bunk. Thinking back, I remember looking at thermal models that showed only a few percent of an overall resistance of a 50W, 100mm^2 die, cooled using a dual fan heatsink/spreader combo, was in the die itself. So even if you eliminate that completely (sheer exaggeration) benefits will be no where near 30%. Mani

To: Daniel Schuh who wrote (21373)	12/2/2000 8:52:27 PM
From: Bill Jackson	Respond to of 275872

Dan, I thought the pure stuff made less heat to begin with, all other things being equal. Something to do with electrons flying along clear ways with less wobbles. The silicon is a pure crystal and the assorted isotopes will all form the same crystal, however the small variations caused by different isotopes might manifest as slight disturbances in the flow of electrons, such a disturbance causes heat. We ned a physics type here. Bill

To: Daniel Schuh who wrote (21373)	12/3/2000 2:20:15 AM
From: Ali Chen	Respond to of 275872

<With current flip-chip packaging, the active area of the silicon is on the heat sink side of the package, right?> Not exactly. Active transistor area is on the surface that faces the package substrate, or pin side. The heat sink is attached to the other side of chip. The chip itself is about 0.8mm thick, therefore the heat must be conducted across the silicon. Now, P = k * S * Dt/Dx, where P - dissipated power, Watts; k is the thermal conductivity (0.8 W/cm/C for silicon), S is the chip area, cm2, Dt is the temperature difference C, Dx is the thickness of the chip. Assuming 100W uniformly on a 1 cm2 chip of 0.1cm thick, we can get the temperature difference across the die: Dt = P * Dx /k /S = 100*0.1/0.8/1=12 C For a thermally bad chip layout with "hot spots", the local junction temperature is proportionally higher: if a local power density is 200W/cm2, the hot spot will be about 24 C above the outer chip surface temperature. Therefore the Si-28 claims look slightly exagerrated - with 50% better conductivity you can shave only few C, and not anywhere close to 30. Of course, everything depends on their definitions and power density assumptions... Regards, - Ali

To: Daniel Schuh who wrote (21373)	12/3/2000 4:50:11 AM
From: pgerassi	Read Replies (3) \| Respond to of 275872

Dear Daniel: You have it 180 degrees out of phase with reality. With flip chip you create the die in the normal manner. That is with active areas in tubs embedded into the top of the wafer. Then at the top metalization layer you add solder balls at all the contacts spread over the active area of the die. The die (chip) is then flipped so that it faces the pin side of the package (bottom) thus, the name flip chip package. the solder balls then contact the pins on the package plane. This increases the number of pins that a particular die can connect to. The heat sink is thus against the reverse layer and the heat goes from the active areas through the wafer and then to the heat sink. Semiconductors have a lower thermal conductivity than metal so much of the loss comes from the silicon of the thickness of a wafer between the active regions on the "pin" side and the heat sink side. This material counts for about 50 to 80% of the thermal resistance between the active junction temperature and the air (most of the reason is the small area of the die compared to the large fin or pin area where the air blows past. From common physics class the temperature drop depends on the heat flow per cross section and the bulk resistance of the material. For a Thunderbird of 120 sqmm and a heat flow of 55W (watts), the heat flow density is 45.7W/sqcm. If the wafer is 1mm thick and the thermal conductivity of common silicon is .8W/cmC, The wafer will cause a thermal drop of (45.7W/sqcm)(.1cm)/(.8W/cmC) or 5.7C. Most good heatsinks are rated at degrees C drop per watt radiated or C/W. A rating of .35 to .5C/W is considered very good. In this case, the drop is (55W)(.35 C/W) or 19.3C. This causes a total drop of 5.7+19.3 or 25C or about 23% of the total is caused by the bulk resistance in today's CPUs not a tiny fraction anymore Mani, even more when exotic cooling methods are used that replace HSFs. In the matter of defect density, a significant fraction occurs because of contamination in the material, another in the slight difference in atom spacing for the three common isotopes, and lastly the smoothness of the crystallization growth rates (clumps of a single isotope would cause greater strain between clumps of different isotopes). The first is minimized due to the methods typically used to make sure that one isotope is selected in the resulting material. These also would reduce further contaminants that cause the defects in the resulting crystal. The second reduces strains and increases regularity which decreases defects. The third reduces defects by eliminating most anomalies within the crystal structure (transistions cause strain, strain causes defects). Just because they are chemically similar does not mean that they are physically similar. Heavy water still reacts like regular water but freezes at a slightly different temperature and sounds travel faster IIRC. Wafer manufacture depends on physical properties, not chemical ones since, ideally, the material is composed of one element. BTW, Mani, in years past when the thermal power generated by CPUs was much smaller, heat sinks with ratings of 1 to 2C/W were far more common. At that time the die bulk caused less of the resistance than the packaging and the heatsink itself. Only the move to active heatsinks, the removal of packaging material between the die and the heatsink, and higher power CPUs in both senses of the phrase has caused the thermal conductivity of the silicon in the bulk wafer (substrate) to be a higher percentage of the problem. It is exacerbated when fluid or gas cooling methods are used, due to their high thermal transport away from the back of the die due to the cooling material (the hot cooling material is physically moved away from the die and the cold cooling material is moved toward the die) being moved past it. This places almost all of the thermal resistance in the bulk die itself. Here a 40% increase in conductivity will drop the temperatures 30% or allow the power usage to rise by the same amount (or a little of both)(This would allow Kyrotech to take a 1.4GHz Palomino on normal silicon and run it at 2.5GHz). Pete