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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: THE WATSONYOUTH who wrote (21920)	12/7/2000 11:55:28 PM
From: Ali Chen	Read Replies (1) \| Respond to of 275872

Watson-Y, <There are already indications that AMD's .13um process might be 6 months or more behind Intel.> Could you elaborate on these indications? In contrast to common-joe opinion, there is tremendous body of evidence that AMD process development was always ahead of Intel. That was the only AMD surviving tool - make copies, slightly better and cheaper. What has changed now, when AMD has independent and competitive design, and even has made some profit? Regards, - Ali

To: THE WATSONYOUTH who wrote (21920)	12/8/2000 12:18:40 AM
From: milo_morai	Respond to of 275872

From what Jerry said in Last CC was 130nm copper was in the works and 130nm and SOI for Clawhammer was in the works. Doesn't that imply to you that he has two processes going at the same time as he stated Ponies on 130nm copper and hammer family only on SOI? M.

To: THE WATSONYOUTH who wrote (21920)	12/8/2000 12:24:45 PM
From: pgerassi	Respond to of 275872

Dear Watsonyouth: Wire loading has many effects with the linear scale of dimensions. First the capacitance is proportional to the length and width assuming that the thickness between layers does not change. But, to make the overall length between junctions scale linearly, you must decrease the thickness between metal layers. This increases the capacitance by an amount proportional to the inverse of the thickness so, overall capacitance decreases linearly with the inverted scaling ratio. Resistance of the wire increases by that same ratio yielding a cutoff frequency being the same no matter the scaling factor. Also, the inductive effects stay constant as long as the scaling affects all dimensions equally. This yields an upper limit to the maximum frequency that stays constant. Where this is relative to the operating frequency is unclear. Also you forget that the channels are most affected by the parasitic capacitance and carrier injection or depletion. They are the closest to the substrate and thus have a large effect wrt switching speeds and a minor effect wrt off state current. Granted, this is typically only a concern to mixed signal RF VLSI projects but with microprocessors already at microwave frequencies, it will being to haunt CPU development. Also the reduction in Vcc cannot go on to much longer as the difference between logic state 1 and logic state 0 voltages begins to near the thermonic noise voltage of 25mV. Once you get near this limit, the SNR drops to unusability and before that quantum effects begin to appear. When that happens, designs are going to get very tough as a number of things that designers take for granted will no longer be true and simulation times will increase greatly (quantum simulation is very much harder and computationally expensive). Quantum effects begin to appear at about 100nm (0.1 micron). You can reduce thermonic noise voltage by cooling the chips ala Kyrotech. I think that SOI becomes more of a factor as geometries get smaller. Pete