1: Intel-ADI's new 2.5G/3G architecture
2: New low-power graphics chips for handhelds.
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ADI, Intel roll DSP core in wireless
thrust
By Patrick Mannion
EE Times
(12/08/00, 6:31 p.m. EST)
MANHASSET, N.Y. — Intel Corp. and Analog Devices
Inc. (ADI) this week rolled out the much-anticipated fruit
of their 21-month collaboration, claiming their Micro
Signal Architecture processor core goes beyond today's
digital signal processors in merging DSP and
microcontroller features to handle the demands of
upcoming wireless systems.
But the companies provided little technical meat to support
their claims (See also "Intel and ADI unveil joint DSP
architecture" for more information). Indeed, the core is
already coming under fire for allegedly delivering
essentially what's already present in existing DSPs. The
partners also may face an uphill battle in attracting
third-party software support for a new instruction set in a
crowded field.
Today's DSPs are ill-equipped to handle the high data rates and
emerging multimedia traffic on 2.5- and third-generation wireless
systems, said Analog Devices' chief executive, Jerry Fishman. "Feedback
from our customers has told us that current-generation DSPs are not
satisfying their needs, and they can't be upgraded to do so."
That's why the two companies joined forces "to realize a new DSP
architecture that could meet the new demands," Fishman said.
The Micro Signal Architecture includes multimedia extensions and
performance primitives designed to speed the processing of audio,
video, image and voice signals, along with dynamic power management
to extend the battery life of portable systems. Additionally, the core
combines frequency scaling and voltage scaling, a scheme said to up
battery life by varying power consumption according to the demands of
the application.
However, the lack of any real performance details or hard specifications
makes it unclear how the core compares with established DSPs such as
Texas Instruments Inc.'s C55x and the StarCore SC140 from the
two-year-old Lucent and Motorola joint venture. Both of these offerings
pack features similar to those of the Micro Signal Architecture.
Techniques like frequency scaling and dynamic power management are
already widely used, analysts and observers said.
"Making aggressive claims on performance, without details, leaves a
little bit of a sense that they're playing catch-up," said Jeff Bier, general
manager of DSP research firm Berkeley Design Technology Inc.
(Berkeley, Calif.). "And the lack of numbers supports this. Either they
don't know, or they don't think [the figures are] particularly good."
"Until detailed performance descriptives become available, it's all just
buzz words," said Paul Marino, director of Motorola's DSP Core
Technology Center.
The new core will initially be available at 300 MHz and 600 million
multiply-accumulate operations (336 Mips) on an 0.18-micron process.
The architecture can be extended to more than 1 GHz and 2,000 Mips,
said Ron Smith, president and general manager of Intel's Wireless
Communications and Computing Group, all while operating at about 1
volt.
Products based on the core will appear separately from ADI and Intel
"sometime in 2001," said ADI chief executive Fishman.
However, some in the industry questioned that road map. Intel and ADI
canceled a planned discussion of their architecture at this year's
Embedded Processor Forum, leading to questions about availability, and
the lack of hard details at last week's announcement in New York
underscored those concerns. ADI was "significantly late" in delivering
both its Hammerhead and TigerSharc DSPs, said analyst Bier, "and
TigerSharc was significantly under performance predictions. So, maybe
they're being cautious [this time]."
At its initial 300-MHz speed, the new core will match the currently
shipping StarCore SC140. TI's C55x is now shipping at 160 MHz, but
"we'll be shipping 200 MHz by [the first quarter of] next year and 300
MHz by midyear," said Mark Mattson, worldwide C5000 product
manager at TI.
The core consists of two multiply-accumulate units (MACs), two
arithmetic logic units (ALUs) and shifter functions. Each MAC is capable
of performing a 16-bit x 16-bit multiply in every cycle, with
accumulation to a 40-bit result. The dual 40-bit ALUs operate on 8-, 16-,
32- or 40-bit data. The architecture can be scaled up or down to include
more or fewer MACs and ALUs, said Smith.
The Micro Signal Architecture has a set of data and pointer registers for
dealing with RISC-type instructions. "Any instruction can operate on any
of the registers, there are no specific tie-ins from instruction and
register," said ADI DSP architect Aaron Bauch. While running control
instructions, both data and address registers are 32-bit registers. "So it
looks very much like a 32-bit RISC with 32-bit addresses with a flat
4-Gbyte address space," Bauch said.
For DSP control instructions, "the user can feed any upper or lower
16-bit value into any other MAC, giving flexibility in where you feed
data from and to," he said. "So for various algorithms, programmers
have pretty much the data path they need.
'Clean-sheet architecture'
"We're talking a clean-sheet architecture here, with all the orthogonality
and programming model of a standard RISC instruction set," Bauch
continued. "But integrated into that instruction set you also have the DSP
capability and hardware of a best-in-class, dual-MAC 16-bit DSP
without compromises on either side. There's no need for code
partitioning, message passing or data sharing, thereby eliminating very
complex structures."
Bauch also pointed to the Linux port. "This shows it's not your classic
DSP architecture," he said. "It is one that can run robust, complex
system code and at the same time gives you all the DSP capability that
you need."
Intel and ADI have marshalled software support for the new
architecture. Third-party developers to date include CMX Systems,
Eonic, Hellosoft, Hitex Development Tools, Lineo and Realogy.
Information is available at the Joint Development Web site.
Performance and architectural elegance may not be enough to establish
the new part, however. The real problem, said analyst Strauss, is
dislodging long-term relationships like TI's with Nokia and Ericsson.
Nokia, for example, designs its own chips using TI's cores. "They're
joined at the hip," Strauss said.
To date, no OEM partnerships stemming from the Intel-ADI alliance
have been announced.
One potential advantage for ADI and Intel is that the TI parts are
single-sourced, said Bier at Berkeley Design. "Customers don't want to
get locked into one vendor," Bier said. "With Intel and ADI, there could
potentially be multiple sources, although it's hard to see what their
respective marketing strategies will be and who will be their customers."
Fishman said ADI will pursue the general-purpose DSP market, using
the new core as its flagship in the 16-bit arena. Intel will favor
applications in line with its StrongARM processor family as part of the
company's Personal Internet Client Architecture.
Another advantage claimed by the two companies is C/C++
programming. "Up to 80 percent of code developed for the Micro Signal
Architecture can be done in C/C++," Intel's Smith said. "This speeds
time-to-market and widens the potential pool of developers, thereby
making more code available."
Nonetheless, said analyst Bier, "designers still can't easily migrate their
existing assembly-language code from existing ADI processors, or for
that matter from earlier processors from other vendors. For TI's C55x,
on the other hand, [migration] was never an issue, since it's
code-compatible with the whole C5000 platform."
TI's Mattson questioned ADI's ability to support yet another line of
DSPs. "How can they support Sharc and TigerSharc, which are
incompatible on the floating-point side, and the 218x and 9x, which are
incompatible with the new Micro Signal Architecture?" he asked. "They
will have a lot of architectures to support. The customer response will be
interesting." The C/C++ programmability will help, but "that still leaves
20 percent in assembly, and that's not going to be able to be ported
over," said Mattson.
For mobile applications, few benchmarks are as critical as power
consumption. Intel and ADI incorporated dynamic power control in
their core using gated-clock circuitry. Fishman said this scheme allows
the core to achieve a 10x battery life extension while operating at
one-third the performance level of competitive designs.
Also lowering power demands is the combination of frequency and
voltage. Frequency scaling, which can be done using clock dividers and
phase-locked loops, is not new, said analyst Bier. But "with voltage
scaling added, you get the benefit of the square relationship between
voltage and power, thereby adding greatly to the linear power reduction
achieved through frequency scaling."
But the idea of voltage scaling may have passed its prime, said Kevin
Kloker, director of the StarCore architecture. "With today's IC processes
and battery voltages, there's not a whole lot you can gain with voltage
scaling," he argued. "This would have been really advantageous in the
days of 3.3- or 5-V devices."
While the voltage range for any part using the new core depends on the
implementation, ADI's Bauch argued that "at the power levels needed for
portable devices, the square relationship between voltage and power
makes scaling worth implementing, regardless of the process."
Bier said that in 2.5G and 3G wireless communications systems, "the
power consumption of the processor is not the designer's biggest
problem. There will be a lot of fixed-function or other technology
required to implement wideband terminals," and the processor "may in
the end not be the main power consumer in a terminal."
For multimedia, the Micro Signal Architecture incorporates instruction
set enhancements that cater specifically to video, imaging, audio and
voice streams. In addition, a hierarchical memory structure with a
bandwidth of 2.4 Gbytes/second speeds memory accesses and overall
processing.
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Graphics engine startup touts
smart partitioning for handhelds
By Junko Yoshida
EE Times
(12/08/00, 6:37 p.m. EST)
SAN MATEO, Calif. — Startup MediaQ Inc. has
developed a graphics engine for low-power wireless
Internet appliances built around an advanced architecture
that allows handheld systems to run Web-browsing and
rich multimedia applications while dramatically reducing
system-level power drain.
This development kicks off what industry watchers expect
will be a series of moves by chip vendors in 2001 toward
smarter partitioning of processing tasks for power-stingy
handhelds.
STMicroelectronics recently told EE Times it plans to roll
out in mid 2001 a Pocket Multimedia Platform for mobile
phones and PDAs, with a special emphasis on clever
system-level partitioning for system-on-chip (SoC)
platforms. "To design such a power-conscious platform,
by far the most important thing is the right partitioning,"
said Philippe Geyres, corporate vice president at
STMicroelectronics and general manager of the consumer and
microcontroller groups.
Lower-power cores and processors on an SoC are a start, but more
important are issues like off-chip vs. on-chip memory, memory access,
bus bandwidth and I/Os, Geyres said.
Both MediaQ (Santa Clara, Calif.) and ST also are predicting a new
trend for handheld solutions, in which a traditional single-processor
architecture will give way to the use of multiple DSP and processor
cores that intelligently share multimedia processing tasks.
STMicroelectronics plans to offer on its Pocket Multimedia Platform
flexible combinations of a number of cores, including SH-5 processors
and very long instruction-word cores for deeply embedded multimedia
functions.
"Customers don't care how many cores we use [in a system]. What
matters in a power-conscious platform is the best system architecture
that can minimize bus traffic and memory access," said Geyres.
For its part, MediaQ in January will sample the MQ1132 and MQ1100.
Each combines a 64-bit 2-D graphics engine, a liquid-crystal-display
interface, a USB device controller and embedded memory in a single
device. The MQ1132, additionally, offers USB host and serial peripheral
interface controllers and an I2S stereo-audio interface.
"Our goals have been to design a new handheld system architecture that
can achieve high performance while consuming less power," said
Manish Singh, product manager at MediaQ.
Developing such a balanced system architecture is critical at a time when
"lower-power, display-centric connected appliances are becoming so
popular," said Sunder Velamuri, vice president of marketing and
co-founder of MediaQ. "Handheld devices are expected to provide
instant response to all these new applications and yet they need to be
power-stingy," he added. Connectivity to wireless or wired peripherals is
also a must.
Processor-intensive applications like multimedia, office applications and
games "place increasingly heavy demands on the capabilities of today's
single-processor handheld architectures," said Alex Slawsby, analyst for
smart handheld solutions at International Data Corp. As these demands
begin to outstrip processor capability, a need arises to off-load some
functions from the main processor, such as video or audio processing,
he added. Solutions such as MediaQ's let the processor focus on core OS
functions. "The result will be increased device capabilities, which will
allow for the further evolution of smart handheld-device applications
and functionality," Slawsby said.
In designing their new chips, MediaQ's engineers — many of whom
designed chips for portable products at companies such as S3, Chips &
Technologies, Cirrus Logic and LSI Logic — paid special attention to the
efficient use of scarce handheld-system resources like CPU cycles,
memory bandwidth and power.
The 2-D graphics-acceleration chips off-load memory-intensive graphics
operations from the CPU. And by integrating 256 kbytes of SRAM, the
MediaQ ICs also reduce interrupt traffic to the CPU by buffering
multiple I/O transactions in on-chip SRAM.
The chips are designed to conserve memory-bus bandwidth and system
power. For graphics operations such as display refresh, for example, the
CPU and DRAM/system memory can be turned off when using the
MQ1132, thus cutting system power drastically. System power
consumed during refresh can be as low as 35 milliwatts. By contrast, as
much as 200 mW is consumed if only a CPU such as the StrongARM is
used, with no separate graphics chip, said Singh. The MQ1132 also
buffers peripheral traffic to reduce memory-bus utilization and lower
system power consumption.
The key to the MediaQ chips lies in the company's ability "to provide a
significant power reduction over current solutions while at the same time
providing optimal performance," said Adrienne Downey, research
analyst at Semico Research. MediaQ's "target for power management is
the LCD, which is the largest power consumer in a portable device."
Downey added, "By taking over the graphics frame buffer and
peripheral interface functions, combined with the increased embedded
memory to handle these functions, [MediaQ's] device frees up
bandwidth between the CPU and system memory for applications and
the operating system."
The chips support the major portable operating systems such as Palm
OS, Linux, WindowsCE and Epoc32, and a variety of CPUs. The latter
include the Hitachi SH-7750 and SH-7709, Intel's StrongARM,
Motorola's Dragonball, NEC's VR-4100 and Toshiba's TX-39x2
processors. Such flexibility would only "make MediaQ's chips easier and
less costly to design-in than other solutions," analyst Downey observed.
The MQ1100 is priced at $10.95 per unit for volumes of 10,000 per
month, while the MQ1132 sells for $12.95 in similar quantities. |
