To: Jim Oravetz who wrote (2566 ) 12/19/2000 3:55:33 PM From: Scrapps Respond to of 2882 Octal ADSL chip set weighs in at 1.3 W per port By Patrick Mannion EE Times (12/19/00, 1:58 p.m. EST) MANHASSET, N.Y. — Stepping up to the DSL central-office challenge of maximum ports at minimum power and footprint, Tioga Technologies has announced its PeakADSL octal central-office ADSL chip set with a per-port footprint and power consumption of 1.4 inches2 and 1.3 watts. Tioga said the level of density and low power the solution achieves enables multiple-tenant DSL access multiplexers, digital loop carriers and multitenant-unit vendors to deliver equipment to service providers that meets the demand for large-scale and fast-growth DSL deployment. In turn, Tioga said, the service providers can address the voracious demand for higher bandwidth from millions of Internet users worldwide. While the company's optimism in terms of DSL demand might seem misplaced — considering the recent competitive local exchange carrier (CLEC) turmoil in DSL — Tom Sennhauser, president and chief executive officer of Tioga (San Jose, Calif.), said the recent turmoil simply symbolizes the lack of equilibrium in the food chain from chip makers through CLECs and incumbent LECs to the customer. "There were too many CLECs and a shakeout was inevitable," he said. "Our expectations at the chip level are that growth will continue in 2001, though at levels more realistic than what had been overly hyped in 2000." To kick off 2001, Tioga will sample its PeakADSL chip set in January, and it expects to reach price points under $20 late in the year. The set comprises the TA1080 octal ADSL transceiver and the TA2040 quad analog front end (AFE). Combined with line-driving circuitry, it provides a complete solution for eight or more full-rate ADSL lines. The TA1080 transceiver supports discrete multitone (DMT) line code to T1.413 Issue 2, ETSI TS 101 388, ITU G.992.1 (including Annexes A, B and C) and ITU G.992.2. It has eight independent transceivers optimized for CO operation with bit rates of a minimum of 3 Mbits/second upstream and 10 Mbits/s downstream. Each transceiver includes a Teak DSP core from the DSP Group Inc., a microcoded DMT engine, framer and data interfaces, interleave memory and object code for a complete management/control API. Sennhauser said, "There is no need for external memory, and we have found that features such as the ability to run the Utopia II interface and the serial interface in dual latency mode to be particularly appealing to customers." Sennhauser also pointed to the fact that no host intervention is required on startup, allowing users to implement a hostless line card using the serial interface. The TA1080 supports category-II ASDL functionality, including Trellis coding and echo cancellation, and comes with a complete software control stack. The TA2040 quad-AFE is actually based on a Fujitsu part, modified to interface seamlessly with the TA1080. It has four independent analog transmit and receive channels supporting G.dmt and G.lite. Each channel contains a 15-bit D/A converter with associated anti-imaging filters, a 15-bit A/D converter with anti-aliasing filter and a programmable gain-summing amplifier. All analog signal paths are differential. A clock multiplier and bandgap references are incorporated on-chip, as are a parallel data interface, a serial interface and integrated transmit interpolation filters. The on-board automatic gain control has a range of 0 to 48 decibels for each receive channel. Though much has gone into reducing the power consumption of the transceiver and the AFE, the effort pales next to the power required by the line drivers, which in this case are from Analog Devices or Elantec. Sennhauser estimates the power consumed by those drivers at roughly 60 percent of the total per port. "Thankfully," he said, "there are new generations of drivers about to hit the market that should consume half the power required by current devices." The TA1080 transceiver uses a 1.8-V, 0.18-micron CMOS process and comes in a 272-pin BGA package, while the TA2040 uses a 3.3-V, 0.35-micron CMOS process and comes in a 216-pin enhanced FBGA. Both have an operating temperature range of --40 to +85 degrees C. eetimes.com