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To: Goutam who wrote (22322)	12/12/2000 4:10:55 PM
From: Petz	Read Replies (1) \| Respond to of 275872

goutama, do we have any idea what Intel's cost basis is on GSPX, LNUX, NUAN and NUFO is? Also, I asked a few questions on the Intel reports a while back. Message 14965691 TIA Petz

To: Goutam who wrote (22322)	12/13/2000 1:57:06 AM
From: ptanner	Respond to of 275872

Goutama, Re: "Here is my updated info on Intel Capital transactions..." Do there need to be some adjustments to the Intel Capital Portfolio? I will not make any unless specifically directed by you. Seems Intel still has a ways to go to reach even the reduced goal for the quarter. Especially since their cost basis in the stocks sold, while perhaps very low, was not zero. -PT

To: Goutam who wrote (22322)	12/14/2000 12:42:40 PM
From: Daniel Schuh	Read Replies (1) \| Respond to of 275872

Intel stock price cheap? You must be joking theregister.co.uk Goutama, I thought you might enjoy this minor exercise in due diligence picked up by the Register. Not quite up to your standards, but still somewhat entertaining. Especially the signoff. Strip out non-recurring investment gains (a whopping $3.3 billion for the first nine months of this year) and Intel's forward P/E rockets to 30, Auerback reckons. This looks expensive, considering that the last time Intel's average annual P/E was 30 was in "1983 and from 1988 to 1996 (when the personal computer industry was booming) the average annual P/E ratio ranged from 11 to 14", he points out. Now the PC industry is "stagnant and Intel faces a huge competitive threat from AMD". Auerback signs off by urging Lex to do its homework. "Just because this nonsense about Intel is repeated endlessly by Wall Street analysts does not make it true." ® Cheers, Dan.

To: Goutam who wrote (22322)	12/14/2000 2:41:31 PM
From: EricRR	Read Replies (1) \| Respond to of 275872

Read this story with a critical eye: Intel also took a look at the execution trace cache, a feature designed to compensate for the long instruction pipeline by caching only decoded micro-ops. It's a key part of the memory subsystem that reduces decode latency, and engineers were leaning toward making it bigger rather than smaller, Boggs said. Compromising, Intel kept the size of the trace cache at 12,000 instructions and developed in instruction a micro-op "compression algorithm" so that micro-ops can be stored in the cache using fewer bits. That gave the execution trace cache "essentially the same performance and less die size," Boggs said. Translation- The Trace cache didn't work as well as we thought, so we needed a patch. To compensate for the L3 loss, Intel doubled the density of the L2 cache to 256 kbytes. It also cut the L1 cache size in half to 8 kbytes and reduced its load capacity to one per clock, thereby reducing latency, Boggs said. eet.com