Smaller Die and Bigger Wafers...
By Joanne Itow, Semico
Silicon Strategies
(12/11/00 15:48 p.m. EST)
The Year of the Dragon is going to go down in semiconductor history as one of the highest growth years but in addition, Semico believes it is a pivotal year for the rollout of new technology. In the last month, there have been a number of announcements touting production-ready 300mm wafers and the offering of 0.13-micron processes. One of the more unusual things about the shift in leading edge technology is that two of the most prominent players in this arena are the two dedicated foundry providers, TSMC and UMC.
0.13-micron Announcements
In March 2000, TSMC announced that its first group of advanced technology partners had begun new designs based on its 0.13-micron process. In October TSMC began offering 0.13-micron prototyping through its multi-product wafer prototyping service, CyberShuttle. By 2001, TSMC expects to be running 30 percent of its CyberShuttle program on the 0.13-micron process.
But TSMC is not the only one in the running. In November, Intel announced successful completion of its 0.13-micron logic technology development on SRAMs and microprocessors. Intel's 18Mbit SRAM is 2X smaller than previous generations. Intel is developing its 0.13-micron technology with copper interconnect on 6 layers and plans to ramp this technology in eight fabs over the next two years. This transition is being planned at Intel's logic fabs in Portland, Arizona, Santa Clara, and Leixlip (Scotland), both existing and new facilities.
And of course, not to be out-done by anyone, IBM then rolled out its 0.13-micron process in a series of two announcements. The first was made by the technology partnership which includes Infineon, UMC and IBM. The first announcement unveiled the foundry process, 8SF, a 0.13-micron 'true' low k-dielectric using a resin trademarked by Dow Chemical called SiLK. One week later, IBM announced its own 9S process which includes SiLK and Silicon on Insulator. IBM claims this as the premier process for high performance, low power applications. This process is not available to its foundry partners but IBM says that based on the interest level so far, the 8SF and 9S processes will be integrated into the mainstream at faster rates than other new technologies.
300mm Announcements
Along with the move to smaller process geometries, the foundries are moving quickly to 300mm wafers.
In November, TSMC made a big splash by announcing it began processing the industry's first customer product on 300mm wafers. TSMC is right on schedule with its plan to ramp 300mm production at Fab 6 to 4,500 wafers per month in 2001. In addition, its first 300mm fab, Fab 12, in Hsin-Chu will begin wafer starts in the fourth quarter 2001. Fab 14 is the second 300mm fab and is under construction next to Fab 6 in Tainan. The newest addition is the recently approved Fab 15, which is planned to begin construction before the end of 2001. Sounds like a lot of capacity, especially when each fab will produce approximately 25,000 wafers per month, an equivalent of over 55,000 8-inch wafers. In addition, TSMC announced the development of a 0.13-micron mixed signal RF test chip. The company is on schedule for 0.13-micron production by Q4 2001.
In the first week of December, Trecenti Technologies, the joint venture foundry established by Hitachi, Ltd and UMC announced the successful run of 4M and 8M SRAM chips using 0.18-micron technology. This pilot run was two months ahead of schedule and Trecenti expects to produce volume runs by March 2001.
IBM has always stated that the company was not going to be the first with a 300mm fab. It wasn't until October 2000 when IBM announced a $5 billion capital investment plan which included some concrete plans for a 300mm fab. About half of the $5 billion is being dedicated to the retrofit of a fab in East Fishkill. IBM plans to install equipment in the beginning of 2002, begin ramping in the third quarter of 2002, and start volume production in the first quarter of 2003.
Smaller Die, Larger Wafers...
This might cause some observers to get nervous about the need, or should I say reduced need, for more capacity.
To put the die size issue in perspective, if all the industry's SRAM units could be processed at Intel's cell size of only 2.09 micron squared, less than half the amount of silicon would be necessary to arrive at the same number of units.
So is it true? Should equipment vendors start worrying about an over capacity situation? Semico says, no need to be worried, yet. Although spending may not be as robust as it was this year, we do not see a major glut of capacity for several reasons.
The foundry market is still expected to grow by over 20 percent over the next five years.
Click the above image to enlarge...
One of TSMC's major customers, Altera, is processing an FPGA with a significantly larger die size than the reported 0.13-micron SRAM. While an 8-inch wafer can produce several thousand SRAM units per wafer, some of the leading edge PLD products still only get 20-50 die per wafer on their high-end products.
In addition, DRAM vendors are proceeding cautiously with its plans for 300mm fabs. Not only is the market causing some DRAM manufacturers to pull in the reins on expansion plans, it's also being reported that the transition to 300mm and 0.13-micron is not going to be a walk in the park. The transition will be challenging and won't happen overnight. And its not just the DRAM vendors. There is only a handful of companies that are investing over $2 billion in capital investment. With a few exceptions, most companies have paired down their fab expenditures and are investing with a foundry partner.
For all these reasons, Semico still holds to its original forecast. Even with these major announcements of advancing technology, in the short term, Chicken Little has nothing to cry about. Semico foresees a slowdown and slight over capacity situation in 2002, but these advancements are all a part of the industry's progress as defined by Moore's Law. |
