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To: fyodor_ who wrote (22485)12/14/2000 4:51:16 PM
From: dale_laroyRead Replies (6) | Respond to of 275872
 
My guess is that they would only integrate the memory controller. But I also think Clawhammer will be Socket-A.

On the other hand. AMD has said that AGP could hang off the LDT bus. So it is conceivable that both PCI and AGP would hang off the LDT bus.

Anyway, AMD would be fools to integrate the memory controller into Clawhammer before the Rambus lawsuits are settled, unless they were to collaborate with Micron on an entirely new memory standard. Remember, Rambus is currently in the process of suing manufacturers of memory controllers. Any processor with an integrated memory controller would be fair game for Rambus to extort a 5% or higher tribute on the gross sales. Of course, I think they also claim a patent on DDR, so the EV6 bus of Socket-A is also fair game.

The way I see it, Synchronous SRAM was around long before Rambus came into the picture, so the key is to use a Synchronous SRAM cache as a buffer between the processor and the DRAM cells. Thus, for "CAS" access, the processor could use Synchronous SRAM protocols. The DRAM cells could be standard EDO DRAM cells, which are not covered by the Rambus patents, with all accesses other than refresh passing through the integrated SRAM "cache lines".

DDR could be very interesting. The two cores of the Sledgehammer processor could be 180 degrees out of phase with each other. Thus, one core could sample/present a signal on the bus only on the rising clock signal edges while the other core would sample/present a signal on the bus on the falling clock signal edges. At the DRAM device level, one set of Synchronous SRAM buffers would sample/present a signal only on the rising edge of the clock signal, while the other set would sample/present a signal on the falling edge of the clock signal. I think this would be adequately divergent from Rambus's DDR patents to insure immunity from their extortion.