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To: THE WATSONYOUTH who wrote (22718)	12/17/2000 7:57:51 PM
From: milo_morai	Respond to of 275872

Mainstream processors prepare for Level 3 cache By Anthony Cataldo EE Times (12/15/00, 11:39 a.m. EST) eet.com M.

To: THE WATSONYOUTH who wrote (22718)	12/17/2000 8:32:39 PM
From: Dan3	Read Replies (1) \| Respond to of 275872

Re: Intel's take on SOI. Thanks for the link. It's just beyond an abstract, so it's a bit difficult to note the details of what they were actually comparing. I noticed in their conclusion that they explain that it was only after "aggressive reduction in junction capacitance of our bulk CMOS process" that the benefits of SOI reduced to 10% at .1 micron and 16% at .18. (compared to the 25% benefit they originally reported) It sounds as though the inclusion of "aggressive reduction in junction capacitance" of AMD's SOI will put them right back at the 25% performance gain IBM has been reporting. And AMD has said they will be using augmenting their SOI process with low-K. I remember that Intel originally claimed they could use aluminum for .13, then they learned better. Deja Vu? I'm just a layman in this area, what is your take on the possible benefits / lack of benefits? Regards, Dan

To: THE WATSONYOUTH who wrote (22718)	12/18/2000 5:32:08 AM
From: Gopher Broke	Read Replies (1) \| Respond to of 275872

Thanks for the link. A difficult read for the layman, but aren't the researchers a bit too hung up on transistor switching speed? I would have thought that SOI had other benefits that could result in an overall faster running processor and better yields. Doesn't the presence of the insulating plane help with a cleaner delineation of the devices? Isn't it possible to have a thinner insulating layer and so better heat removal from the base of the chip in a FCPGA packaging? One other thought. The conclusion of the Intel researchers seems to be that SOI works great on .18 but by extrapolation it will not be nearly as good on .10. But at these dimensions perhaps some of the relationships they assume are linear become less so? Why did Intel not actually experiment with both processes at .13? IBM did so and they are saying that SOI is a huge advantage.