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To: fyodor_ who wrote (23752)1/2/2001 6:25:23 PM
From: Joe NYCRead Replies (2) | Respond to of 275872
 
Fyo,

(From the same link) - I wonder what this is about:

Low Latency DDR
This presentation will introduce a cost effective DRAM integrated cache architecture that will improve the performance of next generation DDR memory. This presentation reviews the architecture and its benefits to system performance and power management.

Some other noteworthy presentations:

Lightening Data Transport
Enabling I/O and inter-processor communications throughput satisfactory for the demands of next generation platforms. Get a glimpse of the support and infrastructure building within the industry for LDT.

Mobile Platform Strategies
Learn how you can prepare for the upcoming transition to Athlon based mobile platforms. Getting the most from AMD PowerNow technology.